High-Frequency Programmable PECL Clock Gener ator
Features
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Jitter peak-peak (TYPICAL) = 35 ps
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LVPECL output
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Default Select option
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Serially-configurable multiply ratios
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Output edge-rate control
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16-pin TSSOP
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High frequency
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3.3V operation
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For more, see pdf
Introduction
The CY2213 has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The CY2213 is a slave device and can either read or write information on the dataline upon request from the master device.
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