AN4011 - Choosing The Right Cypress Synchronous SRAM
Last Updated: 09/24/2012
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Version: *D
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| This application note gives an overview of Standard Synchronous, NoBL, QDR-II, QDR-II+, DDR-II and DDR-II+ SRAM's. |
Cypress currently manufactures several major synchronous SRAM architectures. The purpose of this application note is to provide a means to determine which architecture is right for a particular application. In so doing, a brief description will be supplied concerning each architecture and each will be contrasted by address/data relationships and significant performance characteristics.
The table below shows the architecture comparison for the different options:
Parameter |
Std. Sync |
NoBLTM |
DDR-II/DDR-II+ |
QDRTM-II/ QDRTM-II+ |
Data Rate |
Single |
Single |
Double |
Double |
Data Bus |
Common I/O |
Common I/O |
Common and Separate I/O |
Separate I/O |
VDD |
3.3V/2.5V |
3.3V/2.5V |
1.8V |
1.8V |
VDDQ |
LVTTL 3.3V/2.5V |
LVTTL 3.3V/3.5V |
HSTL (1.5V/1.8V) |
HSTL (1.5V/1.8V) |
Clock Frequency |
250 MHz |
250 MHz |
333 MHz / 550 MHz |
333 MHz / 550 MHz |
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这些文档仅供参考。赛普拉斯、赛普拉斯管理层、雇员及分销商对翻译错误不承担任何责任。当您在设计开发过程中使用这些文档时，我们强烈建议您参照英文版本。
これらの文献はあくまでもご参考のためのみに日本語翻訳されています。誤訳によるトラブルが発生した場合、Cypress Semiconductor Corp. 全ての子会社、関連会社、役員、従業員、販売代理店は一切の責任を負いかねます。
最新の英語版オリジナル文献を必ずご参照いただくことをお勧め致します。
Spec No: 001-15488;
Sunset Owner: PRIT;
Secondary Owner: VIDB;
Sunset Date: 06/15/21
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