AN6017 - Differences in Implementation of 65 nm QDR™II/DDRII and QDRII+/DDRII+ Memory Interfaces
Last Updated: 08/23/2012
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Version: *C
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This application note covers the differences in implementation of 65 nm QDRII/DDRII devices and QDRII+/DDRII+ Memory Interfaces. More
This document describes the following:
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Description of the QDRII+/DDRII+ devices
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Differences between QDRII/DDRII and QDRII+/DDRII+ functionality and timing
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Design changes that need to be considered by system designers when migrating from QDRII/DDRII to QDRII+/DDRII+ devices
The table below outlines the differences between the QDRII/DDRII and QDRII+/DDRII+ SRAMs
Differences between QDRII / DDRII and QDRII+ / DDRII+
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QDR II / DDRII |
QDRII+ / DDRII+ |
Remark |
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Frequency (PLL enabled)-65nm technology device |
120 MHz ~ 333 MHz
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120 MHz ~ 550 MHz |
Burst of 2 QDRII+/DDRII+ support 333
MHz and Burst of 4 QDRII+/DDRII+
support 550 MHz as highest frequency. |
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Organization |
x8, x9, x18, x36 |
x18, x36 |
- |
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VDD |
1.8 V ± 0.1 V |
1.8 V ± 0.1 V |
- |
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VDDQ |
1.8 V ± 0.1 V or 1.5 V ± 0.1 V |
1.8 V ± 0.1 V or 1.5 V ± 0.1 V |
- |
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Read latency |
1.5 clocks |
2.0 & 2.5 clocks |
QDRII+/DDRII+ read latency is not user selectable. Offered as two different devices. |
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Input clocks |
Single ended (K,K#) |
Single ended (K,K#) |
- |
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Output clocks (C,C#) |
Yes |
No |
- |
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ODT (On-Die Termination) |
No |
Offered in ODT and Non ODT versions |
- |
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A0 (DDR B2) |
Yes |
No |
- |
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A0, A1 (DDR B4) |
Yes |
No |
- |
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Echo clock number |
1 Pair |
1 Pair |
Echo clocks are single ended |
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PKG |
165 ball FBGA |
165 ball FBGA |
- |
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Individual byte write (BW0#, BW1#) |
Yes |
Yes |
- |
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Spec No: 001-16631;
Sunset Owner: PRIT;
Secondary Owner: NJY;
Sunset Date: 06/06/11
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