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AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide

Last Updated: 09/21/2012
Version: *F


Cypress Quad Data RateTM-II (QDRTM-II),QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for communication and data storage applications. The purpose of this application note is to assist designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.

 

(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)


这些文档仅供参考。赛普拉斯、赛普拉斯管理层、雇员及分销商对翻译错误不承担任何责任。当您在设计开发过程中使用这些文档时,我们强烈建议您参照英文版本。

これらの文献はあくまでもご参考のためのみに日本語翻訳されています。誤訳によるトラブルが発生した場合、Cypress Semiconductor Corp. 全ての子会社、関連会社、役員、従業員、販売代理店は一切の責任を負いかねます。 最新の英語版オリジナル文献を必ずご参照いただくことをお勧め致します。




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Spec No: 001-15486; Sunset Owner: PRIT; Secondary Owner: VIDB; Sunset Date: 06/15/21

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