AN43380 - HSB Operation in nvSRAMs
Last Updated: 10/03/2012
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Version: *C
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| This application note describes the internal architecture and functionality of Hardware STORE Busy (HSB) pin of Cypress nvSRAMs. |
Introduction
Cypress’ nonvolatile synchronous random access memory (nvSRAM) cell integrates a fast speed SRAM cell and a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) based nonvolatile cell into a single nvSRAM cell. The nvSRAM combines the best features of SRAM and EEPROM and makes it the fastest and the most reliable nonvolatile memory solution in the industry. The SRAM is read from and written to it an infinite number of times, while independent nonvolatile data resides in the nonvolatile elements.
This application note explains the HSB# pin internal architecture and its behavior during the device operation.
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Related Application Notes:
Domain Tags: Async, Serial, I2C, SPI, Non Volatile Memories, non-RTC, RTC
Related Knowledge Base: HSB, I2C, nvSRAM, Parallel, Serial, SPI, Vcap, Async, Datasheet, BUSY
Spec No: 001-43380;
Sunset Owner: ZSK;
Secondary Owner: PSR;
Sunset Date: 09/22/11
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