This application note considers the interface issues between the Cypress CY7B923/933(HOTLink)transmitter/receiver and Cypress Clocked FIFOs.This note is divided into two sections:HOTLink Transmitter-Clocked FIFO interfaces, and HOTLink Receiver-Clocked FIFO interfaces.The transmitter interface section provides a simple design example that uses a state machine to control the HOTLink-FIFO interface.A state transition diagram for the controller is provided.Critical path timing analysis is then discussed for this design example.The derived critical path equations and their critical datasheet parameters are provided and explained.A timing diagram is shown to help illustrate these critical timing relationships.
The HOTLink Receiver-FIFO interface section also includes a simple design example.A simple state machine controls this interface.The state machine addresses design issues such as reframing the serial data,BIST(Built-In Self-Test), and programming clocked FIFOs.These issues are discussed in detail.A state transition diagram is included.Critical path timing equations are derived and the advantages of pipelining the interface are discussed.Timing waveforms are shown to help illustrate the critical timing relationships.
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