AN44517 - Design Recommendation for Battery Backed SRAMs Using Cypress MoBL® SRAMs
Last Updated: 11/23/2012
|
|
|
Version: *E
|
Battery Backed SRAM's (BBSRAM's), also called NVRAM's by system designers, are an important part of applications that require any kind of data backup in the event of a power failure. The block diagram below illustrates a simple FPGA/microcontroller-based application that contains a shared memory bus (Flash memory SRAM), a supervisor chip and a battery. In the event of a power failure, the battery-supervisor combination acts as a power backup for the SRAM, to ensure its contents are undisturbed. The supervisor chip places the SRAM in disable mode (standby) to reduce power consumption and extend battery life. This ensures data integrity and power savings.
The attached Application Note discusses Design Considerations that need to be taken into account when using Cypress MoBL SRAM's in these battery backed applications.
|
这些文档仅供参考。赛普拉斯、赛普拉斯管理层、雇员及分销商对翻译错误不承担任何责任。当您在设计开发过程中使用这些文档时，我们强烈建议您参照英文版本。
これらの文献はあくまでもご参考のためのみに日本語翻訳されています。誤訳によるトラブルが発生した場合、Cypress Semiconductor Corp. 全ての子会社、関連会社、役員、従業員、販売代理店は一切の責任を負いかねます。
最新の英語版オリジナル文献を必ずご参照いただくことをお勧め致します。
Related Application Notes:
Domain Tags: Interface, Async, Voltage, Dual supply
Related Knowledge Base: Voltage Regulator, Data Retention, Low Power, Power Consumption, SRAM, Data Integrity, Async, Battery Backup, uPower, MoBL
Spec No: 001-44517;
Sunset Owner: RAME;
Secondary Owner: AJU;
Sunset Date: 10/06/11
|
|