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Sync SRAMs

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Results 1 - 10 of 10
Title Customer Rating Updated
AN58815 - Advantages of 65 nm Technology over 90 nm Technology QDR® Family of SRAMs

Not yet rated 		01/17/13
AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details
AN80555 details the implementation and timing details of the RH QDR®II+ Interface Controller targeted for the Xilinx Virtex-5QV family of devices. The given reference design example uses built-in Virtex-5QV structures to achieve an aggregate data throughput of 36-GB per second.
Not yet rated 		12/02/12
AN69702 - 72-Mbit RHQDRII+™ Power Modes

Not yet rated 		09/25/12
AN4011 - Choosing The Right Cypress Synchronous SRAM
This application note gives an overview of Standard Synchronous, NoBL, QDR-II, QDR-II+, DDR-II and DDR-II+ SRAM's.
Not yet rated 		09/24/12
AN1090 - NoBL™: The Fast SRAM Architecture
AN1090 describes the operation of NoBL™ SRAMs and outlines how it is suitable for networking applications.
Not yet rated 		09/21/12
AN46982 - PLL Considerations in QDRII/II+/DDRII/II+SRAMS
AN46982 provides an overview of the operation of QDR-II/II+/DDR-II/II+ SRAMs in PLL disabled mode.
Not yet rated 		09/21/12
AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide

(4.3/5) by 3 users 		09/21/12
AN42468 - On-Die Termination for QDR™II+/DDRII+ SRAMs
AN42468 discusses on-die termination (ODT) scheme, implementation, advantages and power calculation for the QDR™II+ and DDRII+ family of Synchronous SRAMs on the 65-nm technology devices.
(4/5) by 1 user 		09/11/12
AN6017 - Differences in Implementation of 65 nm QDR™II/DDRII and QDRII+/DDRII+ Memory Interfaces

(4/5) by 2 users 		08/23/12
AN4017 - Understanding Temperature Specifications: An Introduction

(5/5) by 1 user 		08/08/12
Results 1 - 10 of 10