|
Title
|
Customer Rating
|
Updated
|
Reference Schematic Design Recommendation for QDR-DDR II/II+/Xtreme SRAMs - KBA84386
Question: How to get a recommended reference schematic design for QDR-DDR II/II+/Xtreme products?
|
Not yet rated
|
11/20/12 |
Input Jitter Requirements for 65 nm QDRII/II+/DDRII/II+ Device Family - KBA84380
Question:What are the input jitter requirements for 65 nm QDRII/II+/DDRII/II+ device family?
|
Not yet rated
|
11/20/12 |
How to Resolve QDR-DDR II/II+/Xtreme Verilog Model Simulation Error Using Synopsys VCS - KBA84385
Question:Why Synopsys VCS gives incorrect simulation result with QDR-DDR II/II+/Xtreme verilog models?
|
Not yet rated
|
11/20/12 |
Unused BWSb Pin Termination for ODT Enabled QDR-II+/DDR-II+ SRAM Devices - KBA82774
Question: Explain termination options for unused BWS pins.
|
Not yet rated
|
11/07/12 |
Termination of Input pins in Sync SRAMs - KBA82779
Question: Do all input pins need pull up resistors for termination ?
|
Not yet rated
|
11/07/12 |
I/O Switching Power for Sync SRAM - KBA82208
Question: Is the IDD (VDD operating supply current) current specified in the Sync SRAM datasheets sum of both the core current and I/O current?
|
(4/5) by 1
user
|
10/18/12 |
Removal of External Pull-up Resistor (R) to Vt on D bus, BWSb, and K/Kb Clocks for QDR II+ and DDRII+ ODT Parts - KBA82936
Question: Can the external pull-up resistor (R) to Vt on D bus, BWSb, and K/Kb clocks be removed for QDRII+ and DDRII+ ODT enabled parts?
|
Not yet rated
|
10/10/12 |
Back to Back Write in Synchronous SRAMs - KBA82781
Question: Can /WE be kept LOW during back-to-back write or does it has to be toggle on every write on this back-to-back transaction in Synchronous SRAMs?
|
Not yet rated
|
10/03/12 |
Footprint / Landpattern of an SRAM?
Where can i get recommended footprint / Landpattern for standard packages?
|
Not yet rated
|
09/12/12 |
Types of Burst Modes in Single Data Rate Synchronous SRAMs - KBA80733
Question: What are the types and functions of burst modes in Standard Sync/NoBL SRAMs (single data rate synchronous SRAMs)?
|
Not yet rated
|
06/26/12 |
Burst Operation for QDR and DDR Synchronous SRAM Families - KBA80731
Question: How does the burst feature work in QDR and DDR SRAMs, and what are its advantages?
|
Not yet rated
|
06/26/12 |
Advantages of Burst Modes in Single Data Rate Synchronous SRAMs- KBA80732
Question: What are the advantages of burst modes in Standard Sync/NoBL SRAMs (Single data rate synchronous SRAMs)?
|
Not yet rated
|
06/26/12 |
Maximum Junction Temperature and Power Consumption Calculator
How can I find the power consumption, maximum junction temperature and absolute maximum temperature of an SRAM part ?
|
(4/5) by 1
user
|
05/07/12 |
Address pin numbering in QDR II SRAMs
Why are the address lines not numbered in the pin out section of the QDR II datasheet?
|
Not yet rated
|
04/18/12 |
Why do your address pins not match Samsungs or other vendors?
Parts by other vendors are obsolete. In the Cypress equivalent part the address and data lines are different. Can i use Cypress part without changes in firmware?
|
Not yet rated
|
04/16/12 |
Considerations when migrating from Samsung to Cypress QDRII/DDRII SRAMs
What are the considerations that need to be made when migrating from Samsung to Cypress QDRII/DDRII SRAMs
|
Not yet rated
|
03/29/12 |
Vss and Vcc clarification
Which pin is ground: Vcc or Vss?
|
Not yet rated
|
03/13/12 |
Floating data input on CMOS SRAM
I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?
|
Not yet rated
|
03/13/12 |
Do Address pins have internal Pull-up or Pull-down circuits?
Do you have internal pullups or pulldowns on your address pins so that they may be left floating?
|
Not yet rated
|
03/13/12 |
Do you have Land Patterns or layouts
Do you have a recommended land pattern for my Cypress device?
|
Not yet rated
|
03/13/12 |
Does
What does the 'T' at the end of some part numbers mean?
|
Not yet rated
|
03/13/12 |
DRAM Availability
Does Cypress make DRAM?
|
Not yet rated
|
03/13/12 |
How to Submit Parts for FA
How can I send a device in for failure analysis?
|
Not yet rated
|
03/13/12 |
DLL Considerations in QDRII/DDRII SRAMs
How do QDRII/DDRII SRAMs behave in DLL disabled mode
|
Not yet rated
|
03/07/12 |
Address and I/O Pin Order Flexibility for the Standard Synchronous and NoBL™ SRAMs
Address pin and I/O pin order
|
Not yet rated
|
03/07/12 |
Echo clocks in QDR-II?
Why do QDR II devices have Echo clocks?
|
Not yet rated
|
03/06/12 |
Constraints and Interchangeability of Data and Address pins in Sync SRAMs
What are the design constraints in the interchangeability of data and address pins in Sync SRAMs?
|
Not yet rated
|
03/06/12 |
Part Number Decoder for Cypress NoBL SRAMs
Where can I find Part Number Decoder for NoBL SRAMs ?
|
(5/5) by 1
user
|
01/01/12 |
Moisture Sensitivity Level (MSL) of Cypress Parts
How do I find Moisture Sensitivity Level (MSL) of Cypress parts?
|
Not yet rated
|
09/08/11 |
Data Valid Window Calculation
How do you calculate the Data Valid Window in QDRII SRAMs?
|
(5/5) by 1
user
|
09/01/11 |
Back to Back Write in Synchronous SRAMs
Can /WE be kept LOW during back to back write or does it has to be toggle on every write on this back to back transaction in Synchronous SRAMs?
|
Not yet rated
|
09/01/11 |
Connect the ADV/nLD- and the BW- pins to a static level
Is it possible to connect the ADV/nLD- and the BW- pins to a static level? Do I need them to toggle during normal operation?
|
Not yet rated
|
09/01/11 |
Are the echo clocks CQ/CQ# differential clocks?
Are the echo clocks CQ/CQ# differential clocks?
|
Not yet rated
|
09/01/11 |
Input Jitter in Synchronous SRAMs
Does Synchronous SRAM like when interfaced with an FPGA sensible to cycle jitter OR does it accept everything as long as timing requirements are met?
|
Not yet rated
|
09/01/11 |
Echo Clocks Usage QDR and DDR Synchronous SRAM families
What is the Echo clock?
|
(5/5) by 1
user
|
09/01/11 |
QVLD pin usage
Explain the use of QVLD signal in QDR-II+/DDR-II+ SRAM's?
|
Not yet rated
|
09/01/11 |
Power up sequence and the use of DOFF# in QDRII/II+ and DDRII/II+ SRAMs
What is the power up and initialization sequence to be followed for the QDRII/II+ and DDRII/II+ devices?
|
Not yet rated
|
09/01/11 |
Events causing Soft Error Rate (SER) in Sync SRAMs
What are the various events causing Soft Error Rate (SER) in Sync SRAMs?
|
Not yet rated
|
09/01/11 |
QDRII/DDRII/QDRII+/DDRII+ clocking
How should be QDRII/DDRII/QDRII+/DDRII+ clocking ?
|
Not yet rated
|
09/01/11 |
Part Number Decoder for Standard Sync SRAMs
Where can I find Part Number Decoder for Standard Sync SRAMs?
|
(5/5) by 1
user
|
09/01/11 |
Pull up value of "MODE" pin on CY7C1360C
What is the value of pull up resistance on the "MODE" pin on CY7C1360C?
|
Not yet rated
|
07/01/11 |
cross-section drawings and thickness ?
Where do I Request a cross-section drawing with layers labeled and nominal thickness that can be identified?
|
Not yet rated
|
06/26/11 |
Termination guidelines for interfacing QDR II SRAMs with Virtex FPGAs
Do you recommend any specific termination guidelines for interfacing QDR II SRAMs with Virtex FPGAs?
|
Not yet rated
|
06/24/11 |
SRAM Environmental Testing
Where is the environmental and mechanical testing data available.
|
Not yet rated
|
06/20/11 |
Burst and NoBL SRAM access
What do you mean by 2-1-1-1 and 3-1-1-1 accesses which you show for Sync Burst and NoBL SRAMs?
|
Not yet rated
|
06/18/11 |
Simultaneous Reads and Writes on the CY7C1302 QDR
On the QDR SRAM, can I give a READ and WRITE command simultaneously?
|
Not yet rated
|
06/18/11 |
JTAG pins floating
If we do not want to use the JTAG, can we leave those pins floating?
|
Not yet rated
|
06/18/11 |
Capturing data with a single clock using DDR SRAMs
I am using a FPGA with a DDR interface that will support capturing data off both edges of a single clock. Can I use only one of the CQ and CQ* pairs and capture both edges?
|
Not yet rated
|
06/18/11 |
Effect of Speed, Package Type and Die Revisions on Models
When browsing the website for SRAM models, I have noticed that certain speeds have the same models while other models are package or revision specific. How do you know which models are affected by revisions, packages, or speed of the device.
|
Not yet rated
|
06/18/11 |
K and K\ signals in DDR
Are K, K\ are differential signals in DDR?
|
Not yet rated
|
06/18/11 |