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Title
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Customer Rating
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Updated
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Footprint / Landpattern of an SRAM?
Where can i get recommended footprint / Landpattern for standard packages?
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Not yet rated
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09/12/12 |
Why do your address pins not match Samsungs or other vendors?
Parts by other vendors are obsolete. In the Cypress equivalent part the address and data lines are different. Can i use Cypress part without changes in firmware?
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Not yet rated
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04/16/12 |
Vss and Vcc clarification
Which pin is ground: Vcc or Vss?
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Not yet rated
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03/13/12 |
Floating data input on CMOS SRAM
I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?
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Not yet rated
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03/13/12 |
Do Address pins have internal Pull-up or Pull-down circuits?
Do you have internal pullups or pulldowns on your address pins so that they may be left floating?
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Not yet rated
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03/13/12 |
Do you have Land Patterns or layouts
Do you have a recommended land pattern for my Cypress device?
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Not yet rated
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03/13/12 |
Does
What does the 'T' at the end of some part numbers mean?
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Not yet rated
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03/13/12 |
How to Submit Parts for FA
How can I send a device in for failure analysis?
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Not yet rated
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03/13/12 |
/BUSY & /INT signal architectures: Migrating from RAM28 to RAM42 technology
What is the difference in the IO architecture for /BUSY and /INT signals between the RAM28 and the RAM42 Dual Port SRAMs?
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Not yet rated
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02/13/12 |
/BUSY Signal in Dual Port SRAMs
/BUSY signal functionality in Dual Port SRAMs
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Not yet rated
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02/07/12 |
Lead Free (Pb-free) Dual Port/FIFO/Quad Port Part Number Change
Question: What changes are made to the Lead Free (Pb-free) part numbers for specialty memory (Dual Port/FIFO/Quad Port) products?
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Not yet rated
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12/28/11 |
Clock requirement when no read or write accesses are occurring in FullFlex DPRAMs
Question: Does the clock always have to be provided to the device even when no read or write accesses are occurring in FullFlex DPRAMs?
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Not yet rated
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12/28/11 |
Upgrading the 4-Meg (CY7C0852V/AV) Dual-Port to a 9-Meg (CY7C0853V/AV) Dual-Port
What are the pin considerations while upgrading from a 4-Meg (CY7C0852V/AV) Dual-Port to a 9-Meg (CY7C0853V/AV) Dual-Port?
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Not yet rated
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12/01/11 |
Cypress 100-Pin TQFP Land Pad Geometry
- What are the dimensions of the feet in the 100-pin TQFP package?
- What size should the pads on my board be for a 100-pin TQFP device?
- Suggestions for how to lay out board?
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Not yet rated
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10/11/11 |
Premature PCI cycle end
What happens on a premature cycle end for the PCI-DP, e.g. by making SELECT inactive before the fourth DWORD?
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Not yet rated
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10/11/11 |
Accessing Operations Registers and Shared Memory
- Are there any timing differences between the register access and shared-memory access?
- Do the same rules apply for reading and writing to the operations registers versus the shared memory?
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Not yet rated
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10/11/11 |
Arbitration register
- How is the arbitration register used in the PCI-DP?
- Does the arbitration register prevent collisions?
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Not yet rated
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10/11/11 |
External Vcc Clamps
Are external e.eV IO Clamps needed for the PCI-DP?
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Not yet rated
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10/11/11 |
Interfacing 5V dual-ports with both 5V and 3.3V processors
- Can I power the 5V dual-port with a 3.3V supply (accepting a reduction in speed)?
- I need to interface the dual-port to 5V parts and to 3.3V parts. Is this going to work safely?
- If the two processors attached to the dual-port have different I/O standards (for example, one processor is TTL and one is CMOS), can I still use your dual-port?
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(4/5) by 1
user
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10/11/11 |
Minimum / maximum read and write pulse widths
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Not yet rated
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10/11/11 |
Clearing interrupts in the Host Interrupt Event Status Register
- How do I clear interrupts in the Host Interrupt Control and Status Register?
- How do I clear interrupts in the Local Processor Interrupt Control Status Register?
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Not yet rated
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10/11/11 |
Shared memory arbitration
- How do you prevent collisions in the PCI-DP?
- Is there on-chip arbitration?
- What happens if both the local bus and the PCI bus try to access the same memory location at the same time?
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Not yet rated
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10/11/11 |
NOP cycle in Cypress Dual-Ports
- What is the NOP cycle in the Read Write Read waveform in dual-ports?
- What does NOP stand for?
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(3/5) by 2
users
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10/11/11 |
Pin to pin compatibility issues of Cypress dual-ports
In the IDT device IDT7006L25J, which is a 16K x 8 DPRAM, pins 2 and 33 are No Connect (NC) whereas the correspnding pins in CY7C006A have A14L and A14R for those pins respectively. Is the Cypress part pin-to-pin compatible?
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Not yet rated
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10/11/11 |
Accessing the EEPROM
- How to check the access the serial EEPROM attached to the PCI-DP?
- Is there a way to access (read / write) the boot EEPROM?
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(2.5/5) by 2
users
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10/11/11 |
DualPort: Using Extra Bits for Parity
- Standard bus sizes are 8-bits, 16-bits, 32-bits or 64-bits. Why are Cypress dual-ports offered in 9-bit, 18-bit, 36-bit, and 72-bit versions?
- What are the "extra" bits in the data bus used for?
- Are the extra bits parity bits?
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(4/5) by 1
user
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10/11/11 |
Memory Cell Architecture of Cypress Dual-Ports
- What is the construction of each memory cell?
- Are Cypress dual-ports "true" dual-ports?
- Are dual-port cells different than regular SRAM cells?
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Not yet rated
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10/11/11 |
Soft Reset
- How does soft reset work in the PCI-DP?
- How do you trigger a soft reset?
- What is the difference between a regular and soft reset?
- What happens to the Operations Registers during soft reset?
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Not yet rated
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10/11/11 |
I2C interface problems
Why does SCL not toggle for the PCI-DP?
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Not yet rated
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10/11/11 |
Configuring the PCI-DP from the local bus processor
- Can you configure the PCI-DP from the local bus processor instead of the SEEPROM?
- Are the operations registers accessible from the local bus?
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Not yet rated
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10/11/11 |
PCI-DP inserting wait states
Does the CY7C09449PV always insert at least one wait state?
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Not yet rated
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10/11/11 |
Device to support 5V Vcc 32bit/33MHz PCI for expansion card
Is there a device to support 5V Vcc 32bit/33MHz PCI for expansion card?
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Not yet rated
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10/11/11 |
8 bytes of I/O space in memory
What are the 8 bytes of I/O space used for in the PCI-DP?
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Not yet rated
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10/11/11 |
Moisture Sensitivity Level (MSL) of Cypress Parts
How do I find Moisture Sensitivity Level (MSL) of Cypress parts?
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Not yet rated
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09/08/11 |
Load Capacitance of Tri-State Data bus of many SRAMs connected together
What will be the load capacitance of a Tri-State Data bus when more than one SRAM busses are connected together?
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Not yet rated
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09/01/11 |
Semaphore Value in Asynchronous Dual-Ports
- What are the uses of Semaphore latches?
- How are semaphore values read on the I/O bus?
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Not yet rated
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06/27/11 |
cross-section drawings and thickness ?
Where do I Request a cross-section drawing with layers labeled and nominal thickness that can be identified?
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Not yet rated
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06/26/11 |
SRAM Environmental Testing
Where is the environmental and mechanical testing data available.
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Not yet rated
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06/20/11 |
FIFOs vs Dual-ports
When is a FIFO used instead of a dual port? How do I select between a FIFO and dual-port for my application?
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(3/5) by 1
user
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06/11/11 |
Aggregate bandwidth and throughput of synchronous dual-ports
- How do you calculate bandwidth with dual-ports?
- What is the throughput of a particular dual-port?
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Not yet rated
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06/11/11 |
Using multiple devices to create a wider data path for synchronous dual port SRAM's
How can multiple dual-port devices be combined to create a wider data path?
Can I width cascade multiple dual-ports?
How would I set up the dual-port for width expansion?
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Not yet rated
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06/11/11 |
Depth and width expansion affect on board-level timing
How does memory depth and width expansion affect board-level timing?
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(5/5) by 1
user
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06/11/11 |
CY7C08xxV Read Cycle Latency
- Why is there no FT/PL pin in some of the synchronous dual-ports?
- What is the latency associated with read operations?
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Not yet rated
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06/11/11 |
Battery backed solutions for CY7C08xxV dual-ports
Why is the standby current rating (Isb) on these 2Mb (CY7C0851V) and 4Mb (CY7C0852V) dual-ports so high compared to the 1Mb devices? I would expect the difference in Isb to be fairly linear, but it is, in fact, several orders of magnitude greater. (10 mA vs. 10-50uA).
The complication comes in looking for a battery backup switcher. I've found none of these power monitors can handle >150uA of standby current. Does Cypress have an battery backed solution available for these high-density dual-ports?
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Not yet rated
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06/11/11 |
Simultaneous access in synchronous dual-ports
- Can I write to the dual-port at the same time from both ports?
- What happens when I read and write to the same location at the same time?
- What happens if I read from the same location at the same time?
- If both ports are running off the same clock how may clock cycles after I write can I initiate a read from the same address?
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(4/5) by 1
user
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06/11/11 |
Read-Back of Internal Address Counters for synchronous dual port SRAM's
- How can one see the current state of the internal counter?
- Is there a way to check the state the burst counter?
- Is address readback different for the CY7C08x1V / CY7C08x2V devices?
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Not yet rated
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06/11/11 |
Unused OE# and CE1 Pins
If I am not going to use these pins, what should I do with them?
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Not yet rated
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06/11/11 |
VSS vs. VSSQ for synchronous dual port SRAM's
What is the difference between VSSQ versus VSS in the datasheet?
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Not yet rated
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06/11/11 |
Burst Counter Operation and chip disabled for synchronous dual port SRAM's
If I do a read or write of a number of words and I use the internal counter (ie load the counter start address on the first word and then count after that), but I only give a CE (chip enable) every other clock; will I read data from consecutive address locations every other clock?
An example: For a burst read -- first clock load counter, second clock do nothing, third clock give chip enable and read first data, fourth clock do nothing, fifth clock give chip enable and read second data (next one in memory after first), sixth clock do nothing, seventh clock give chip enable and read third data, etc. Note that output enable and counter enable will always be active. Could you confirm this for me?
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(5/5) by 1
user
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06/11/11 |
Read and Write with Single Internal Counter for Synchronous Dual port SRAM's
What happens if we write on one clock cycle with ADS#, CE# and CNTEN# all low (i.e. load the address counter) and then, on the next cycle we read without ADS# but with CNTEN# (i.e. increment the counter). Will the address we read from be one higher than the one we loaded in the first cycle?
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Not yet rated
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06/11/11 |