|
Title
|
Customer Rating
|
Updated
|
Footprint / Landpattern of an SRAM?
Where can i get recommended footprint / Landpattern for standard packages?
|
Not yet rated
|
09/12/12 |
Why do your address pins not match Samsungs or other vendors?
Parts by other vendors are obsolete. In the Cypress equivalent part the address and data lines are different. Can i use Cypress part without changes in firmware?
|
Not yet rated
|
04/16/12 |
Vss and Vcc clarification
Which pin is ground: Vcc or Vss?
|
Not yet rated
|
03/13/12 |
Floating data input on CMOS SRAM
I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?
|
Not yet rated
|
03/13/12 |
Do Address pins have internal Pull-up or Pull-down circuits?
Do you have internal pullups or pulldowns on your address pins so that they may be left floating?
|
Not yet rated
|
03/13/12 |
Do you have Land Patterns or layouts
Do you have a recommended land pattern for my Cypress device?
|
Not yet rated
|
03/13/12 |
Does
What does the 'T' at the end of some part numbers mean?
|
Not yet rated
|
03/13/12 |
How to Submit Parts for FA
How can I send a device in for failure analysis?
|
Not yet rated
|
03/13/12 |
Moisture Sensitivity Level (MSL) of Cypress Parts
How do I find Moisture Sensitivity Level (MSL) of Cypress parts?
|
Not yet rated
|
09/08/11 |
Semaphore Value in Asynchronous Dual-Ports
- What are the uses of Semaphore latches?
- How are semaphore values read on the I/O bus?
|
Not yet rated
|
06/27/11 |
cross-section drawings and thickness ?
Where do I Request a cross-section drawing with layers labeled and nominal thickness that can be identified?
|
Not yet rated
|
06/26/11 |
SRAM Environmental Testing
Where is the environmental and mechanical testing data available.
|
Not yet rated
|
06/20/11 |
FIFOs vs Dual-ports
When is a FIFO used instead of a dual port? How do I select between a FIFO and dual-port for my application?
|
(3/5) by 1
user
|
06/11/11 |
Aggregate bandwidth and throughput of synchronous dual-ports
- How do you calculate bandwidth with dual-ports?
- What is the throughput of a particular dual-port?
|
Not yet rated
|
06/11/11 |
Using multiple devices to create a wider data path for synchronous dual port SRAM's
How can multiple dual-port devices be combined to create a wider data path?
Can I width cascade multiple dual-ports?
How would I set up the dual-port for width expansion?
|
Not yet rated
|
06/11/11 |
Depth and width expansion affect on board-level timing
How does memory depth and width expansion affect board-level timing?
|
(5/5) by 1
user
|
06/11/11 |
CY7C08xxV Read Cycle Latency
- Why is there no FT/PL pin in some of the synchronous dual-ports?
- What is the latency associated with read operations?
|
Not yet rated
|
06/11/11 |
Battery backed solutions for CY7C08xxV dual-ports
Why is the standby current rating (Isb) on these 2Mb (CY7C0851V) and 4Mb (CY7C0852V) dual-ports so high compared to the 1Mb devices? I would expect the difference in Isb to be fairly linear, but it is, in fact, several orders of magnitude greater. (10 mA vs. 10-50uA).
The complication comes in looking for a battery backup switcher. I've found none of these power monitors can handle >150uA of standby current. Does Cypress have an battery backed solution available for these high-density dual-ports?
|
Not yet rated
|
06/11/11 |
Simultaneous access in synchronous dual-ports
- Can I write to the dual-port at the same time from both ports?
- What happens when I read and write to the same location at the same time?
- What happens if I read from the same location at the same time?
- If both ports are running off the same clock how may clock cycles after I write can I initiate a read from the same address?
|
(4/5) by 1
user
|
06/11/11 |
Read-Back of Internal Address Counters for synchronous dual port SRAM's
- How can one see the current state of the internal counter?
- Is there a way to check the state the burst counter?
- Is address readback different for the CY7C08x1V / CY7C08x2V devices?
|
Not yet rated
|
06/11/11 |
Unused OE# and CE1 Pins
If I am not going to use these pins, what should I do with them?
|
Not yet rated
|
06/11/11 |
VSS vs. VSSQ for synchronous dual port SRAM's
What is the difference between VSSQ versus VSS in the datasheet?
|
Not yet rated
|
06/11/11 |
Burst Counter Operation and chip disabled for synchronous dual port SRAM's
If I do a read or write of a number of words and I use the internal counter (ie load the counter start address on the first word and then count after that), but I only give a CE (chip enable) every other clock; will I read data from consecutive address locations every other clock?
An example: For a burst read -- first clock load counter, second clock do nothing, third clock give chip enable and read first data, fourth clock do nothing, fifth clock give chip enable and read second data (next one in memory after first), sixth clock do nothing, seventh clock give chip enable and read third data, etc. Note that output enable and counter enable will always be active. Could you confirm this for me?
|
(5/5) by 1
user
|
06/11/11 |
Read and Write with Single Internal Counter for Synchronous Dual port SRAM's
What happens if we write on one clock cycle with ADS#, CE# and CNTEN# all low (i.e. load the address counter) and then, on the next cycle we read without ADS# but with CNTEN# (i.e. increment the counter). Will the address we read from be one higher than the one we loaded in the first cycle?
|
Not yet rated
|
06/11/11 |
Timing relationship of OE# to the dual-port
What is the timing relationship between OE# and CE# in synchronous Dual Ports? - How is the output enable signal connected to the clocks?
|
Not yet rated
|
06/11/11 |
Internal Power-On Reset (POR) Circuitry in Synchronous Dual-Ports
Do synchronous dual-ports have internal power on reset circuitry?
|
Not yet rated
|
06/11/11 |
CE not present in some Dual port SRAM's E.g CY7C0853V
- How do I enable and disable this dual-port since there are no Chip Enable (CE#) pins?
- If I have R/W# tied low on one side (always writing), how can I stop it when I need to?
|
Not yet rated
|
06/11/11 |
Data hold time
Data that is read out of a synchronous dual-port holds valid for a minimum period of "tDC". What is the maximum value?
How long will the data read out (Qn) be available on the data lines after the clock edge?
|
Not yet rated
|
06/11/11 |
Aligning byte enables for synchronous dual port
- If I connected a 32-bit processor to a 36-bit wide dual-port, how can I align the byte enables?
- Can I use the byte enables of the 18-bit wide dual-port if my system is only 16 bits?
|
Not yet rated
|
06/11/11 |
Migration from FLEX 72 to FLEX 72-E
- How to migrate from FLEx72 Migration to FLEx72-E ?
- What do the notes on page 2 of the datasheet mean?
- If I do not wish to use these features, what should I do with the pins?
- What do the pins labeled with a note do in the FLEx72-E?
|
Not yet rated
|
06/11/11 |
Partial access to Dual Port mailbox
Does writing or read only to the upper/lower byte (using LB# and UB#) of the mailbox trigger or clear the interrupt flag?
|
Not yet rated
|
06/11/11 |
Data valid period during two consecutive read cycles with the same address
During a flow-through read cycle, your datasheets specify that tCD1 after the rising edge of the read CLK, data is ready to be read. They also specify that the data will remain valid for tDC. My question is what would happen if you perform two flow-through read cycles with the same address consecutively? The datasheet shows a data valid period followed by unknown data followed by the data valid period for the following read. Does this apply to this case? Or will the same valid data from the first read remain on the data lines until the end of the second read cycle?
|
Not yet rated
|
06/11/11 |
Burst Counter Wrap-Around
- What happens when I use the burst counter and reach the very last memory location?
- Does the internal counter return to 0 when I reach the end of the memory array?
- If the burst counter wraps around to 0, will I be able to continuously read the data on every clock cycle or do I have to pause my reading operations?
|
Not yet rated
|
06/11/11 |
Timing and clock skew in synchronous Dual port during simultaneous read and write at same location
What does it mean to violate tCCS when one port is writing and the other reading from the same location?
How does the timing differ depending on whether it is the read or the write that happens slightly before the other?
|
Not yet rated
|
06/11/11 |
Bus Matching in CY7C09569V/CY7C09579V Dual-ports
How do I set up the bus-matching features on my dual-port?
How can I change the bus matching set-up after initial power-up?
|
Not yet rated
|
06/11/11 |
FullFlex - Variable Impedance Matching/Variable Impedance Sensing in Fullflex dual ports
What is Variable Impedance matching (VIM), Variable impedance Sensing (VIS)? How does it work, what are its effects and what are resistor tolerances?
|
Not yet rated
|
06/11/11 |
FullFlex - Echo clocks and their timing benefits
Explain Echo clocks for FullFlex Dual ports SRAM's? What are their timing benefits?
|
Not yet rated
|
06/11/11 |
Configuring pipelined vs. flow-through mode after power up
Can the Flowthrough/Pipeline mode be reconfigured after power-up for some Full flex dual port SRAM's?
|
Not yet rated
|
06/11/11 |
FullFlex - Power sequencing for the Fullflex
How is Power Sequencing done for the Fullflex Dual Ports?
|
Not yet rated
|
06/10/11 |
CY7C0852V BSDL and JTAG
CY7C0852V BSDL and JTAG Questions: - What is wrong with the Pause-DR state? - How do you prevent going into the Pause-DR state? - What happens during JTAG testing when I enter Pause DR? - What happens to the CY7C0852V JTAG Chain in PAUSE-DR State?
|
Not yet rated
|
06/10/11 |
Stand-by Power Consumption of the CY7C0853V
What is the ISB (stand-by current) value for the CY7C0853V?
How can I save power on the 9M dual-port?
|
Not yet rated
|
06/10/11 |
SRAM powerup data output
If a read occurs on power up of an SRAM device, does the memory deliver highs, lows or high-z, since no data was ever loaded into the memory.
|
Not yet rated
|
04/04/11 |
tLZOE and tHZOE demystified
Timing specification on some datasheets mentions timings tLZOE(min) and tHZOE(max) as 5 and 20 ns respectively. But foot note 15 mentions at any given temp and voltage tHZOE is less then tLZOE. Please clarify the interpretation of this?
|
Not yet rated
|
04/04/11 |
UL94V-0_compliance
Are all of your devices UL94V-0 compliant?
|
Not yet rated
|
04/04/11 |
Extra 4 or 2 bits if 32/16 bits are used in x36/x18 part.
what do I do with the extra 4 or 2 bits if I want to use only 32/16 bits in a X36/X18 part?
|
Not yet rated
|
04/04/11 |
Ram 4 and Ram 5 on your Reliability report
What does Ram 4 and Ram 5 on your Reliability report mean?
|
Not yet rated
|
04/04/11 |
extra 2 bits for parity check?
Why do we have 2 extra bits for parity checking.
|
Not yet rated
|
04/04/11 |
Mean time between failures?
How to calculate mean time between failures (MTBF)?
|
Not yet rated
|
04/04/11 |
Parity during read and write
How is parity generated during reads and write?
|
Not yet rated
|
04/04/11 |
Failure In Time (FIT)
Where do I find the FIT value for a particular device?
|
Not yet rated
|
04/04/11 |