|
Title
|
Customer Rating
|
Updated
|
Generation of FIFO Empty and Full Flags - KBA85082
Question: How are FIFO empty and full flags generated?
|
Not yet rated
|
04/04/13 |
Footprint / Landpattern of an SRAM?
Where can i get recommended footprint / Landpattern for standard packages?
|
Not yet rated
|
09/12/12 |
Why do your address pins not match Samsungs or other vendors?
Parts by other vendors are obsolete. In the Cypress equivalent part the address and data lines are different. Can i use Cypress part without changes in firmware?
|
Not yet rated
|
04/16/12 |
Vss and Vcc clarification
Which pin is ground: Vcc or Vss?
|
Not yet rated
|
03/13/12 |
Floating data input on CMOS SRAM
I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?
|
Not yet rated
|
03/13/12 |
Do Address pins have internal Pull-up or Pull-down circuits?
Do you have internal pullups or pulldowns on your address pins so that they may be left floating?
|
Not yet rated
|
03/13/12 |
Do you have Land Patterns or layouts
Do you have a recommended land pattern for my Cypress device?
|
Not yet rated
|
03/13/12 |
Does
What does the 'T' at the end of some part numbers mean?
|
Not yet rated
|
03/13/12 |
How to Submit Parts for FA
How can I send a device in for failure analysis?
|
Not yet rated
|
03/13/12 |
Availability of FIFO parts CY7C460, CY7C462, CY7C464 & CY7C466
Question: Where can we look for information on the following FIFO parts CY7C460, CY7C462, CY7C464 & CY7C466?
|
(4/5) by 2
users
|
12/28/11 |
Aggregate bandwidth and throughput of synchronous FIFOs
- How is the aggregate bandwidth of a synchronous FIFO calculated?
- How is the aggregate throughput of a synchronous FIFO calculated?
|
Not yet rated
|
12/28/11 |
Programming the Almost Empty / Almost Full (PAE, PAF) Flags
- How do I program the PAE and PAF flags?
- What is the valid range for PAE and PAF flags?
- How do I store the PAE and PAF values?
|
Not yet rated
|
12/28/11 |
Read Pointer operation in CY7C42x1 FIFOs
- Is the address pointer incremented when REN1 & REN2 are asserted, RCLK is toggled, but OE is not asserted?
- What happens if RCLK is toggled, but only REN1 is asserted (REN2 is not)?
|
Not yet rated
|
12/28/11 |
Tapped Serial Delay Lines Using FIFOs
How can you implement a tapped serial delay line using a FIFO?
|
Not yet rated
|
12/28/11 |
Tying two (unidirectional) FIFO outputs together
Can I safely tie two outputs together in case of depth cascading? or How should I set up my system to switch from one data bus to another when using two FIFOs? or Can I use the output enables (OE#) to switch from one bus to another if they are tied together?
|
Not yet rated
|
12/28/11 |
Moisture Sensitivity Level (MSL) of Cypress Parts
How do I find Moisture Sensitivity Level (MSL) of Cypress parts?
|
Not yet rated
|
09/08/11 |
Load Capacitance of Tri-State Data bus of many SRAMs connected together
What will be the load capacitance of a Tri-State Data bus when more than one SRAM busses are connected together?
|
Not yet rated
|
09/01/11 |
Synchronous FIFO Flag Update Cycle
- What is the Flag Update Cycle?
- Must the FIFO be read to update the empty flag?
- Must the FIFO be written to for the full flag to be updated?
|
Not yet rated
|
06/27/11 |
Usage of the Vcc/SMODE# pin
|
Not yet rated
|
06/27/11 |
cross-section drawings and thickness ?
Where do I Request a cross-section drawing with layers labeled and nominal thickness that can be identified?
|
Not yet rated
|
06/26/11 |
Master Reset cycle
- How to reset the FIFO?
- How to operate /MR?
- What is a proper reset?
|
Not yet rated
|
06/23/11 |
SRAM Environmental Testing
Where is the environmental and mechanical testing data available.
|
Not yet rated
|
06/20/11 |
Read / Write control signals on unidirectional FIFOs
Why is there a read/write control signal (R/W#) on each port for a unidirectional FIFO?
|
Not yet rated
|
06/18/11 |
Writing at the Full Boundary
- What happens if FIFO is continuously write into when Full Flag is asserted?
- My system is set up to continuously write until the FIFO is full. Once it is full, I begin to read out the data. However, it seems like I lose some of the data being written into the FIFO when I do so. RCLK and WCLK are the same. What is wrong?
|
Not yet rated
|
06/17/11 |
Usage of the Output Enable (OE) Signal in Synchronous FIFOs
1. If OE is high, what happens to the data bus?
2. If there is a valid read operation, but OE is high, will the next read operation be the same word or the following word in the FIFO?
3. If OE is high during reset, will the data bus remain in a high-Z state?
4. Is it okay to connect the OE pin to ground?
|
Not yet rated
|
06/17/11 |
Synchronous FIFO architecture
What is the architecture of the Synchronous FIFOs? Is the memory managed by pointers or shifting registers? If the fullness of the FIFO is managed well, is it possible to endlessly read and write?
|
Not yet rated
|
06/17/11 |
Usage of different speed grades in synchronous FIFOs
- Can I replace a -35 device with with a -25 device?
- If the two ports of my FIFO are running at different rates, how do I pick a speed grade for my system?
|
Not yet rated
|
06/17/11 |
Driving REN1 and REN2 together for some families of synchronous FIFO's
- Can I drive /REN1 and /REN2 with the same signal?
- Can I tie Read Enable 1 and Read Enable 2 together?
|
Not yet rated
|
06/17/11 |
Retransmit feature of synchronous FIFO's
- What happens to the data lines when RT is pulsed and during the tRTR time?
- Can a selected block of data be retransmitted?
- What considerations are there for using the retransmit operation?
|
Not yet rated
|
06/17/11 |
Delay buffers using synchronous FIFOs
How can I make a delay buffer that always has x number of words in the buffer?
|
Not yet rated
|
06/17/11 |
Synchronous FIFO Clocks
- Are there any requirements for clock duty cycles?
- Do the clocks have to have 50 percent duty cycles?
- What are the requirements for the clock driving sync FIFOs?
|
Not yet rated
|
06/17/11 |
Output State for the FIFOs
- Can I make the data outputs (Q0 - Q8) to be normally high?
- What is the status of the data outputs after reset?
- What happens to the data outputs when /OE is asserted?
|
Not yet rated
|
06/17/11 |
Driving 3.3V I/Os on a 5V device
- Can I drive 3.3V I/Os into a 5V part?
- What are the minimum input levels for 5V devices?
- Will my 3.3V processor be strong enough to connect to a 5V device?
- Will a -1V undershoot on the inputs cause problems?
|
Not yet rated
|
06/17/11 |
Usage of XI#, XO#, and FL#/RT signals
- What should pin XOn, /XO, RXOn, /RXO, RXIn, /RXI, WXOn, /WXO, WXIn, /WXI, FLn, /FL be tied to if I am not cascading?
- What should these pins be tied to if I am width cascading?
- What should these pins be tied to if I am depth cascading?
|
Not yet rated
|
06/17/11 |
Maximum number of cascaded FIFOs
How many FIFOs can I cascade in depth and by width? What are the considerations?
|
Not yet rated
|
06/17/11 |
Using a FIFO as a transparent device
- Can the FIFO be used transparently?
- Can data written into the FIFO be read straight out?
- Can one tie WCLK and RCLK together?
|
Not yet rated
|
06/17/11 |
Asynchronous vs Synchronous(Clocked) FIFOs
- What is the difference between clocked and synchronous FIFO's?
- What different types of FIFO's are there?
- Why should one prefer one type over another?
|
Not yet rated
|
06/13/11 |
Signal Overshoot / Undershoot
- How does signal overshoot affect FIFO operation?
- How does one fix overshoot/undershoot problems on the board?
|
Not yet rated
|
06/13/11 |
Cypress FIFO Architecture
- How is the FIFO made?
- Is the FIFO memory volatile or non-volatile?
- Is the FIFO memory static or dynamic?
- What is the architecture of Cypress FIFOs?
- Are Cypress FIFOs bubble-through FIFOs?
|
Not yet rated
|
06/13/11 |
General FIFO - Tri-stated signal connected to data inputs
What will happen if we have a tri-state output connected to the input of the FIFO? We are always driving the clock and control inputs; it is only the data inputs that will be receiving a tri-stated floating signal.
|
Not yet rated
|
06/13/11 |
External Master Reset of all Cypress FIFO's
- Is there a built-in reset in Cypress FIFO's?
- Is there POR circuitry in Cypress FIFO's?
- Do I need to reset the FIFO on power up?
|
Not yet rated
|
06/13/11 |
Master Reset problems
- What all things can affect Master Reset?
- Even after following timing specifications for Master Reset, it is not working , why ?
- Will noise on the signal lines affect the functionality of the device.
|
Not yet rated
|
06/13/11 |
Unidirectional vs. Bidirectional FIFOs
What is the difference between unidirectional and bidirectional FIFO's? Why would I use a bidirectional FIFO? How is memory shared in a bidirectional FIFO?
|
Not yet rated
|
06/13/11 |
Using /FF as a Half Full flag in depth cascaded FIFO's
If cascading two FIFO's in depth, can the full flag (/FF) of the first FIFO be used as the half full flag for both FIFO's?
|
Not yet rated
|
06/13/11 |
Replacing asynchronous FIFO's with synchronous FIFO's
- What design considerations are there when converting from an asynchronous FIFO to a synchronous one?
- What is different about designing with synchronous FIFOs?
- Can you operate a synchronous FIFO as an asynchronous one?
|
Not yet rated
|
06/13/11 |
FIFOs vs Dual-ports
When is a FIFO used instead of a dual port? How do I select between a FIFO and dual-port for my application?
|
(3/5) by 1
user
|
06/11/11 |
TCLK when TAP controller disable
To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. If tie high is the same, pull up, just not leave it float.
|
Not yet rated
|
06/09/11 |
SRAM powerup data output
If a read occurs on power up of an SRAM device, does the memory deliver highs, lows or high-z, since no data was ever loaded into the memory.
|
Not yet rated
|
04/04/11 |
tLZOE and tHZOE demystified
Timing specification on some datasheets mentions timings tLZOE(min) and tHZOE(max) as 5 and 20 ns respectively. But foot note 15 mentions at any given temp and voltage tHZOE is less then tLZOE. Please clarify the interpretation of this?
|
Not yet rated
|
04/04/11 |
UL94V-0_compliance
Are all of your devices UL94V-0 compliant?
|
Not yet rated
|
04/04/11 |