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Title
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Customer Rating
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Updated
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AN5042 - Migrating from Cypress FLEx18 / FLEx36® / FLEx72™ Dual-Port SRAMs to FullFlex Dual-Port SRAMs
Updated
AN5042 discusses the features of Cypress's FullFlex Dual-Port SRAM and typical applications for which the devices are ideally suited.
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Not yet rated
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02/07/13 |
AN43593 - Storage Capacitor (VCAP) Options for Cypress nvSRAM
AN43593 discusses the selection criteria for the storage capacitor (VCAP) options for Cypress nvSRAMs. This document also provides a sample list of a few suitable capacitors as guidance.
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Not yet rated
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02/04/13 |
AN58815 - Advantages of 65 nm Technology over 90 nm Technology QDR® Family of SRAMs
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Not yet rated
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01/17/13 |
AN70630 - Event Data Recorder with Controller Area Network using PSoC® 3 and nvSRAM
AN70630 describes how to combine PSoC® 3 with Cypress nvSRAM to build an event data recorder (EDR), which is finding increasing application in automotive. PSoC 3, with its controller area network connectivity and efficient data transfer using direct memory access, helps free the CPU to execute other tasks.
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Not yet rated
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12/20/12 |
AN6081 - Interfacing 90-nm Cypress Asynchronous SRAMs in Legacy Systems
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(3.3/5) by 4
users
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12/19/12 |
AN69061 - Design, Manufacturing, and Handling Guidelines for Cypress Wafer-Level Chip Scale Packages (WLCSP)
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(4.6/5) by 7
users
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12/14/12 |
AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details
AN80555 details the implementation and timing details of the RH QDR®II+ Interface Controller targeted for the Xilinx Virtex-5QV family of devices. The given reference design example uses built-in Virtex-5QV structures to achieve an aggregate data throughput of 36-GB per second.
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Not yet rated
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12/02/12 |
AN44517 - Design Recommendation for Battery Backed SRAMs Using Cypress MoBL® SRAMs
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(5/5) by 1
user
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11/23/12 |
AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates
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(5/5) by 18
users
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11/02/12 |
AN43380 - HSB Operation in nvSRAMs
This application note describes the internal architecture and functionality of Hardware STORE Busy (HSB) pin of Cypress nvSRAMs.
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(5/5) by 1
user
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10/03/12 |
AN6068 - Replacing MRAM with Cypress nvSRAM
AN6068 discusses the key pinout differences between a MRAM and Cypress nvSRAM device.
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Not yet rated
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10/03/12 |
AN6022 - A Comparison between nvSRAMs and BBSRAMs
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Not yet rated
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09/27/12 |
AN69702 - 72-Mbit RHQDRII+™ Power Modes
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Not yet rated
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09/25/12 |
AN64574 - Designing with Serial Peripheral Interface (SPI) nvSRAM
Cypress's serial peripheral interface (SPI) nvSRAM is a high-performance nonvolatile serial memory that offers zero cycle delay write operation and infinite SRAM write endurance.
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Not yet rated
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09/25/12 |
AN4011 - Choosing The Right Cypress Synchronous SRAM
This application note gives an overview of Standard Synchronous, NoBL, QDR-II, QDR-II+, DDR-II and DDR-II+ SRAM's.
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Not yet rated
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09/24/12 |
AN1090 - NoBL™: The Fast SRAM Architecture
AN1090 describes the operation of NoBL™ SRAMs and outlines how it is suitable for networking applications.
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Not yet rated
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09/21/12 |
AN46982 - PLL Considerations in QDRII/II+/DDRII/II+SRAMS
AN46982 provides an overview of the operation of QDR-II/II+/DDR-II/II+ SRAMs in PLL disabled mode.
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Not yet rated
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09/21/12 |
AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide
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(4.3/5) by 3
users
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09/21/12 |
AN42468 - On-Die Termination for QDR™II+/DDRII+ SRAMs
AN42468 discusses on-die termination (ODT) scheme, implementation, advantages and power calculation for the QDR™II+ and DDRII+ family of Synchronous SRAMs on the 65-nm technology devices.
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(4/5) by 1
user
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09/11/12 |
AN66311 - Timing Recommendation for Byte Enables and Chip Enables in MoBL® SRAMs
AN66311 provides timing recommendations for the use of byte enable pins (BHE and BLE) and chip enables (single or dual, as applicable) in select Cypress MoBL® SRAMs. Note that the datasheet should be read before implementing timing recommendations mentioned in this document.
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(5/5) by 1
user
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09/11/12 |
AN61546 - Non Volatile Static Random Access Memory (nvSRAM) Real Time Clock (RTC) Design Guidelines and Best Practices
AN61546 describes the real time clock (RTC) functionality, components selection criteria, and best layout design practices for the nvSRAM RTC design. Design guidelines and best practices advised in this application note are intended to assist customers in designing nvSRAM with RTC functions in their system design and minimize timing errors, which mostly occur due to improper layout design and components selection.
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Not yet rated
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08/27/12 |
AN6017 - Differences in Implementation of 65 nm QDR™II/DDRII and QDRII+/DDRII+ Memory Interfaces
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(4/5) by 2
users
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08/23/12 |
AN6023 - NonVolatile SRAM (nvSRAM) Basics
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(4/5) by 1
user
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08/16/12 |
AN53313 - Real Time Clock Calibration in Cypress nvSRAM
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Not yet rated
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08/15/12 |
AN4017 - Understanding Temperature Specifications: An Introduction
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(5/5) by 1
user
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08/08/12 |
AN15979 - Soft Errors in nvSRAM
AN15979 describes the soft error causes in the memories and how nvSRAM-architecture features and packaging techniques act to reduce soft errors.
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Not yet rated
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07/26/12 |
AN1044 - Understanding Asynchronous FIFOs (with Self-Paced Training Module)
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Not yet rated
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07/26/12 |
AN1042 - Understanding Synchronous FIFOs (with Self-Paced Training Module)
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(5/5) by 1
user
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06/29/12 |
AN1043 - Understanding Synchronous Dual Port RAMs (with Self-Paced Training Module)
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(3.5/5) by 2
users
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06/29/12 |
AN52433 - Advantages of Serial Peripheral Interface (SPI) nvSRAM over SPI EEPROM in Metering Applications
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Not yet rated
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06/26/12 |
AN55663 - Migrating from CY14E256L/STK14C88 to CY14E256LA
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Not yet rated
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06/18/12 |
AN55662 - Migrating from STK14C88-3 to CY14B256LA
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Not yet rated
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06/18/12 |
AN72389 - Migrating from CY14B101P/CY14B512P/CY14B256P to CY14B101PA/CY14B512PA/CY14B256PA
AN72389 provides information for migrating from CY14B101P, CY14B512P and CY14B256P to CY14B101PA, CY14B512PA and CY14B256PA respectively.
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Not yet rated
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06/18/12 |
AN55661 - Migrating from CY14B256L/STK14D88 to CY14B256LA
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Not yet rated
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06/13/12 |
AN68174 - Migrating from Serial Peripheral Interface (SPI) EEPROM to SPI nvSRAM
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Not yet rated
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06/12/12 |
AN5036 - Interfacing Cypress MoBL® Asynchronous Dual-Port to TI OMAP1710 Multimedia Processor
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Not yet rated
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05/09/12 |
AN13842 - Recommended Usage of Byte Enables in Standby Mode for 90 nm x16 MoBL® SRAM Devices
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Not yet rated
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04/10/12 |
AN55659 - Migrating from CY14B101L/STK14CA8 to CY14B101LA
AN55659 gives information for migrating from the nvSRAM parts CY14B101L/STK14CA8 to the CY14B101LA. This application note also lists the parameter differences between the parts and the design considerations when converting existing applications from CY14B101L/STK14CA8 to CY14B101LA.
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Not yet rated
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03/26/12 |
Implementing Interprocessor Communication Using Cypress MoBL(R) Dual-Ports and the Mailbox Registers - AN5074
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Not yet rated
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10/27/11 |
AN5075 - Migrating from Cypress CYDMxxxAxx MoBL(R) Dual-Ports to CYDMxxxBxx MoBL Dual-Ports
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(4/5) by 1
user
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05/10/11 |
AN5093 - Cypress MoBL(R) Dual-Port 100-Ball VFBGA Printed Circuit Board (PCB) Layout Guidelines
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Not yet rated
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05/10/11 |
Interfacing Cypress MoBL® Asynchronous Dual- Port to TI OMAP2420 Multimedia Processor - AN5056
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Not yet rated
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01/25/11 |