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Title Customer Rating Updated
Reference Schematic Design Recommendation for QDR-DDR II/II+/Xtreme SRAMs - KBA84386
Question: How to get a recommended reference schematic design for QDR-DDR II/II+/Xtreme products?
Not yet rated 		11/20/12
Input Jitter Requirements for 65 nm QDRII/II+/DDRII/II+ Device Family - KBA84380
Question:What are the input jitter requirements for 65 nm QDRII/II+/DDRII/II+ device family?
Not yet rated 		11/20/12
How to Resolve QDR-DDR II/II+/Xtreme Verilog Model Simulation Error Using Synopsys VCS - KBA84385
Question:Why Synopsys VCS gives incorrect simulation result with QDR-DDR II/II+/Xtreme verilog models?
Not yet rated 		11/20/12
Unused BWSb Pin Termination for ODT Enabled QDR-II+/DDR-II+ SRAM Devices - KBA82774
Question: Explain termination options for unused BWS pins.
Not yet rated 		11/07/12
Termination of Input pins in Sync SRAMs - KBA82779
Question: Do all input pins need pull up resistors for termination ?
Not yet rated 		11/07/12
I/O Switching Power for Sync SRAM - KBA82208
Question: Is the IDD (VDD operating supply current) current specified in the Sync SRAM datasheets sum of both the core current and I/O current?
(4/5) by 1 user 		10/18/12
Removal of External Pull-up Resistor (R) to Vt on D bus, BWSb, and K/Kb Clocks for QDR II+ and DDRII+ ODT Parts - KBA82936
Question: Can the external pull-up resistor (R) to Vt on D bus, BWSb, and K/Kb clocks be removed for QDRII+ and DDRII+ ODT enabled parts?
Not yet rated 		10/10/12
Back to Back Write in Synchronous SRAMs - KBA82781
Question: Can /WE be kept LOW during back-to-back write or does it has to be toggle on every write on this back-to-back transaction in Synchronous SRAMs?
Not yet rated 		10/03/12
Footprint / Landpattern of an SRAM?
Where can i get recommended footprint / Landpattern for standard packages?
Not yet rated 		09/12/12
Types of Burst Modes in Single Data Rate Synchronous SRAMs - KBA80733
Question: What are the types and functions of burst modes in Standard Sync/NoBL SRAMs (single data rate synchronous SRAMs)?
Not yet rated 		06/26/12
Burst Operation for QDR and DDR Synchronous SRAM Families - KBA80731
Question: How does the burst feature work in QDR and DDR SRAMs, and what are its advantages?
Not yet rated 		06/26/12
Advantages of Burst Modes in Single Data Rate Synchronous SRAMs- KBA80732
Question: What are the advantages of burst modes in Standard Sync/NoBL SRAMs (Single data rate synchronous SRAMs)?
Not yet rated 		06/26/12
Cypress Parts Baking Condition Information
Do Cypress parts require baking? If so, what are the conditions?
Not yet rated 		05/24/12
Country of Origin (COO) Information
Where can I find the Country of Origin (COO) of a Cypress product?
Not yet rated 		05/24/12
Maximum Junction Temperature and Power Consumption Calculator
How can I find the power consumption, maximum junction temperature and absolute maximum temperature of an SRAM part ?
(4/5) by 1 user 		05/07/12
Recommended Reflow for Cypress Parts Information
What is Cypress’s Parts Recommended Reflow?
Not yet rated 		04/20/12
Cypress' Parts Shelf Life Condition Information
What is Cypress’s Parts Shelf Life condition?
Not yet rated 		04/19/12
Address pin numbering in QDR II SRAMs
Why are the address lines not numbered in the pin out section of the QDR II datasheet?
Not yet rated 		04/18/12
Difference between CY14B101K and CY14B101KA
What is the difference between CY14B101K and CY14B101KA?
Not yet rated 		04/16/12
Why do your address pins not match Samsungs or other vendors?
Parts by other vendors are obsolete. In the Cypress equivalent part the address and data lines are different. Can i use Cypress part without changes in firmware?
Not yet rated 		04/16/12
List of obsolete PROM parts
What is the status of PROM parts manufactured by Cypress?
Not yet rated 		04/11/12
Initial value of NVSRAM contents after purchase.
What is the value of the contents of the NVSRAM when the device is initially shipped? Can i assume a fixed set of data in the non-volatile memory of the NVSRAM?
Not yet rated 		04/11/12
Considerations when migrating from Samsung to Cypress QDRII/DDRII SRAMs
What are the considerations that need to be made when migrating from Samsung to Cypress QDRII/DDRII SRAMs
Not yet rated 		03/29/12
ISB2 vs Temp and ISB2 vs VCC for CY62147EV30
Provide the characterization data for ISB2 vs Temp and ISB2 vs VCC
Not yet rated 		03/13/12
MoBL SRAM Definition
What are MoBL SRAMs?
Not yet rated 		03/13/12
Vss and Vcc clarification
Which pin is ground: Vcc or Vss?
Not yet rated 		03/13/12
Battery back up for SRAM's
Does Cypress recommend any lithium battery backup for SRAM's?
Not yet rated 		03/13/12
Floating data input on CMOS SRAM
I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?
Not yet rated 		03/13/12
Do Address pins have internal Pull-up or Pull-down circuits?
Do you have internal pullups or pulldowns on your address pins so that they may be left floating?
Not yet rated 		03/13/12
Do you have Land Patterns or layouts
Do you have a recommended land pattern for my Cypress device?
Not yet rated 		03/13/12
Does
What does the 'T' at the end of some part numbers mean?
Not yet rated 		03/13/12
DRAM Availability
Does Cypress make DRAM?
Not yet rated 		03/13/12
How to Submit Parts for FA
How can I send a device in for failure analysis?
Not yet rated 		03/13/12
DLL Considerations in QDRII/DDRII SRAMs
How do QDRII/DDRII SRAMs behave in DLL disabled mode
Not yet rated 		03/07/12
Address and I/O Pin Order Flexibility for the Standard Synchronous and NoBL™ SRAMs
Address pin and I/O pin order
Not yet rated 		03/07/12
Echo clocks in QDR-II?
Why do QDR II devices have Echo clocks?
Not yet rated 		03/06/12
Constraints and Interchangeability of Data and Address pins in Sync SRAMs
What are the design constraints in the interchangeability of data and address pins in Sync SRAMs?
Not yet rated 		03/06/12
Part Number Decoder for Cypress NoBL SRAMs
Where can I find Part Number Decoder for NoBL SRAMs ?
(5/5) by 1 user 		01/01/12
Recommended PCB Land Pattern for Cypress nvSRAM Packages
Does Cypress provide land patterns for all the nvSRAM device packages?
Not yet rated 		10/03/11
Moisture Sensitivity Level (MSL) of Cypress Parts
How do I find Moisture Sensitivity Level (MSL) of Cypress parts?
Not yet rated 		09/08/11
Interleaved part
Is the P/N CY7C1041DV33 an interleaved part? Are the Logical bits physically adjacent in a RAM array?
Not yet rated 		09/01/11
Pull up resistor on WE# control line of nvSRAM
Why do I need to connect a pull up resistor on WE# control line of nvSRAM? What should be the value of pull up resistor?
Not yet rated 		09/01/11
Data Valid Window Calculation
How do you calculate the Data Valid Window in QDRII SRAMs?
(5/5) by 1 user 		09/01/11
Back to Back Write in Synchronous SRAMs
Can /WE be kept LOW during back to back write or does it has to be toggle on every write on this back to back transaction in Synchronous SRAMs?
Not yet rated 		09/01/11
Connect the ADV/nLD- and the BW- pins to a static level
Is it possible to connect the ADV/nLD- and the BW- pins to a static level? Do I need them to toggle during normal operation?
Not yet rated 		09/01/11
Are the echo clocks CQ/CQ# differential clocks?
Are the echo clocks CQ/CQ# differential clocks?
Not yet rated 		09/01/11
Input Jitter in Synchronous SRAMs
Does Synchronous SRAM like when interfaced with an FPGA sensible to cycle jitter OR does it accept everything as long as timing requirements are met?
Not yet rated 		09/01/11
Echo Clocks Usage QDR and DDR Synchronous SRAM families
What is the Echo clock?
(5/5) by 1 user 		09/01/11
QVLD pin usage
Explain the use of QVLD signal in QDR-II+/DDR-II+ SRAM's?
Not yet rated 		09/01/11
Power up sequence and the use of DOFF# in QDRII/II+ and DDRII/II+ SRAMs
What is the power up and initialization sequence to be followed for the QDRII/II+ and DDRII/II+ devices?
Not yet rated 		09/01/11
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