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Answer: The purpose of this article is to provide a reference schematic for the QDR-DDR II/II+/Xtreme devices. The reference schematics shown in this article is derived from an internal characterization board. Please note that this is an example reference schematic that can be used for design. It is expected that system designers perform signal integrity simulations.

Please refer to “AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide” for different termination schemes, design, and signal integrity guidelines.

The following pages provide a snapshot of the schematics from the internal characterization board for the QDR-DDR II/II+/Xtreme SRAMs. For more information on the QDR-DDR II/II+/Xtreme SRAMs, please refer the respective datasheet in the link, http://www.cypress.com/?id=95.

Reference schematic for QDR-DDR II/II+/Xtreme SRAMs

Figure 1a. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Non ODT) Reference Schematic (From internal characterization board)

Figure 1b. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (ODT) Reference Schematic (From internal characterization board)

Figure 2. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Supply Pins) Reference Schematic (From internal characterization board)

Assumptions

• The reference schematic above is from an internal characterization board. It is recommended to perform Signal integrity simulations with the specific board conditions before finalizing the design.
• Figure 1a and Figure 1b are the reference schematics for all Non ODT and ODT QDR-DDR II/II+/Xtreme SRAMs respectively. As an example if the part is x18 device, then Data pins notation D[x:0] will be interpreted as D[17:0].
• QDRII+/II+Xtreme-DDRII+/II+Xtreme devices do not have the input clocks C and C#
• Non ODT QDRII+/II+Xtreme-DDRII/II+/II+Xtreme devices do not contain ODT pin.
• ODT devices have an On-Die Termination feature for Data inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K and K#). Hence, there is no termination for D[x:0], BWS[x:0] , K and K# pins in Figure 1b. Please refer to “AN42468 - On-Die Termination for QDR™II+/DDRII+ SRAMs”, which discusses on-die termination (ODT) scheme, implementation, advantages and power calculation for the QDR™II+ and DDRII+ family of Synchronous SRAMs on the 65-nm technology devices.
• The value of termination resistor (R) is 50 Ω because most of the designs have 50 Ω characteristic impedance for the trace. The termination resistor value should be equal to the characteristic impedance of the trace.
• An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM, hence RQ value is 250 Ω to match output impedance of 50 Ω in Figure 1a and Figure 1b. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 Ω and 350 Ω, with VDDQ = 1.5 V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.
• Keep termination resistors as close to the device as possible to reduce the stub length and thereby reduce reflections.

Decoupling Capacitor Recommendation for Power Supply Pins
 

• Decoupling capacitors on power supply pins play a significant role to filter noise in the power supply.
• It is recommended to place the de-coupling capacitors need to be placed close to the memory devices for best results.
• Following decoupling capacitors recommendation is from internal characterization board.

Decoupling Capacitors for VDD

Figure 3. Decoupling Capacitors Recommendation for VDD (From internal characterization board)

Decoupling Capacitors for VDDQ

• Please refer to the datasheets for VDDQ value.

Figure 4. Decoupling Capacitors Recommendation for VDDQ (From internal characterization board)

Decoupling Capacitors for VTT

Figure 5. Decoupling Capacitors Recommendation for VTT (From internal characterization board)

Decoupling Capacitors for VREF

Figure 6. Decoupling Capacitors Recommendation for VREF (From internal characterization board)

Please, create a technical support case if you are facing any issue, while creating your design or if you would like Cypress to do a schematic review.