Cypress Perform

Answer: When using CY8CKIT-023 PSoC MFi Expansion Board Kit example projects with PSoC Creator 2.1, it surfaces an incorrect clock setup for CapSense during build. This incorrect clock setup was not shown by previous version of PSoC Creator. The warning that comes during build of example projects states as:

Clock Warning: A clock marked as "Sync" cannot be faster than half the frequency of the clock synchronizing it.

To remove this warning, please do the following in example project:

1. Go to TopDesign of the project.
2. Double click the CapSense component.
3. Under General Tabs, in the Clock Settings, change the Scan Clock from 24 MHz to 12 MHz.
4. Clean and build the project

This change will not impact the CapSense performance much and overall look and feel of CapSense buttons and Sliders will remain same.

The knowledge base article "New clock synchronization check exposes aliased scan rate issue in CapSense" includes more details regarding this.