Cypress Perform

Answer: This is a defect in PSoC Designer™ version 5.2 Service Pack 1(and earlier). For the SmartSense version 1.30, the CapSense® configuration wizard allows only one configuration for R_b, that is, to connect it to P1[1]. But since P1[1] is used as SCL (ISSP clock) line, it is not always possible to use it for R_b.

The defect will be fixed in the future versions of PSoC Designer but for the current version the following workaround can be used:

1. Download the attached “SmartSense.asm”.
2. Copy this file (and replace the old SmartSense.asm) to the following folder:
   C:\Program Files\Cypress\PSoC Designer\5.2\Common\CypressSemiDeviceEditor\Data\Stdum\SmartSense\Ver_1_30\CY8C21034

It should be noted that the configuration wizard will still show the R_b connection to P1[1]. But the hardware connection for R_b gets modified when the API SmartSense_Start() is called in “main.c” of the project. This workaround modifies ACE00CR2, ACE00CR1, ALT_CR0, CMP_GO_EN, PRT1DM0, PRT1DM1, and PRT1DM2 registers in the SmartSense_Start() API. The details of these registers can be found in the Technical Reference Manual (TRM) for CY8C21x34.