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CY8C20xx7 device family support I2C transaction without clock stretching

Last Updated: 06/13/2012
Does the CY8C20xx7 device family support I2C transaction without clock stretching?

 

Yes, the CY8C20xx7 device family implements a 32 byte hardware data buffer, accessible as an I2C slave hence, transactions between the host and the buffer requires 
no clock stretching. This enhanced I2C block is available as the I2CSBUF user module in PSoC Designer SP3/4 and supports 50 KHz, 100 KHz and 400 KHz data transfer speed. Additionally, device can also wake up from sleep based on an I2C address match event. 

Related Categories: CapSense® Controllers



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Sunset Owner: KXP; Secondary Owner: VWA; Sunset Date: 06/13/14