Cypress Perform

Answer: Vddd and Vcca pins are outputs of internal voltage regulator of PSoC 3 and PSoC 5. All the internal digital and analog blocks as well as the CPU core of these chips operate at 1.8-V DC power supply. The internal regulators are present to generate this voltage. The outside connections to Vccd and Vcca pins of PSoC 3 and PSoC 5 depend on the supply voltage to chip. Following are the two possible configurations:

Configuration 1 – Internally regulated mode (Vddd and Vdda > 1.89 V):

This is the default mode of operation. In this mode, the internal regulators are switched ON and they provide power supply to internal blocks of PSoC. In this mode, external power must not be applied to the Vccd or Vcca pins. Both of the Vccd pins should be shorted together and connected to Vssd pin through a parallel combination of 1uF and 0.1uF capacitors. The Vcca pin should be connected to Vssa through a single 1 uF capacitor. Following diagram shows this configuration:

In this case, both Vccd pins should be connected together with shortest possible route on the PCB, preferably under the PSoC chip.

Configuration 2 – Externally regulated mode (Vddd and Vdda between 1.71 V and 1.89 V):

This configuration should be used only when external power supply is between 1.71 V to 1.89 V. In this configuration, Vccd pins should be shorted to Vddd and Vcca pin should be shorted to Vdda. After power up in this configuration, the internal regulators are on by default, and should be disabled to reduce power consumption. Refer PWRSYS_CR0 register from PSoC3 Registers TRM to understand how to disable the internal regulators. Following diagram shows this configuration:

Note that the externally regulated mode is applicable only for PSoC 3 and PSoC 5LP. PSoC 5 does not support this mode since the minimum operating voltage to PSoC 5 is 2.7 V.