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Constraints and Interchangeability of Data and Address pins in Async SRAMs

Last Updated: 09/01/2011

Can I interchange the address pins in Cypress Async SRAMs ? Or Can I interchange the data pins in Cypress Async SRAMs ?

 In Asynchronous SRAMs, the address pins (Ax) can be assigned in any bit order. For instance, pin A15 of CPU can be connected to A0 of SRAM, A10 of CPU to A1 of SRAM etc. Address assignment can be made as dictated by layout or other board-level constraints; there is no restriction from internal SRAM-addressing standpoint, unless otherwise specified in the datasheet.

Likewise, data lines can be assigned in any order, within a specific byte. For instance, D0 of CPU can be connected to D4 of SRAM, D1 of CPU to D6 of SRAM etc. However, the data bit assignment should not cross byte boundaries if byte level accesses are made. For instance, a higher bit data of CPU connected to lower bit data line in SRAM could result in conflict when performing byte-specific (lower byte or higher byte) accesses. If such individual byte-level accesses are not made, routing can extend beyond byte boundaries also.


Related Categories: Async Fast SRAMs


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Sunset Owner: KXP; Secondary Owner: VWA; Sunset Date: 06/15/20
Spec No: None; Sunset Owner: KXP; Secondary Owner: VWA; Sunset Date: 06/15/20