Knowledge Base Article
The same valid data would remain on the data lines until the last read cycle perform to the same address. Since the input address for our dual port memory is exactly the same in both reads, there is not a time where internal circuitry attempts to drive data lines to different states. Therefore that same data will remain on the data lines without any switching glitches. You are free to sample the data lines tDC after the data is first valid in this case.