Data Retention Procedure for Async SRAM's
I am designing a battery backed up SRAM and RTC using Cypress Async SRAM (E.g. CY62128). I will use a supercap for several days of backup time. Should I pull up /CE, /WE, and /OE to VccBATT? What else should be taken into consideration?
Not yet rated
03/26/11
BUSY signals when cascading asynchronous dual-ports
How should I use the BUSY signal in width expansion mode?
Why are there BUSY inputs and BUSY outputs?
Why is there a Master and a Slave dual-port?
Why would I need a slave dual-port?
Endurance Limit of Flash Block
The PSoC1 datasheet says that the endurance limit for a single flash block is 50,000 cycles. Is this limit absolute, or average?
Not yet rated
03/27/11
AMUX Switching Time
What is the total AMUX switching time taking into consideration the multiplexer switch instruction? How much time is involved when an input signal is switched inside an ISR?
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03/27/11
I2C Lines at 1.8V
What should be the GPIO setting for I2C lines when they are used at 1.8V for CY8C2xxxx?
Not yet rated
03/27/11
Drive mode for maximum driving strength
Which drive mode should be used for providing the best possible drive strength? Is it possible to tie multiple lines together in order to drive higher load?
RTC Interrupt at a Specific Time - CY8C22x45
I would like to generate an interrupt from the RTC in CY8C22x45 when the RTC's time equals a preset time. Is the RTC module in CY8C22x45 capable of generating an interrupt at a specific time? If not, how can this be implemented?
Comparision between Asynchronous and Synchronous Dual-Port RAMs
- What are the main differences between Asynchronous and Synchronous dual-port rams?
- What are the advantages and disadvantages of using either one of them?
- Under which circumstances is it better to use Async/Sync?
- Should I use asynchronous or synchronous dual-ports for my application?
- I have a fast processor. Should I use a synchronous or asynchronous dual-port?
Read data problems in synchronous dual-ports
Why is the data read from a synchronous dual-port always the last word written even though the read address is different than the write address?
Not yet rated
03/27/11
Writing data into the dual-port
- After the data is clocked into the sync DPRAM, on which clock is the data actually written to the memory?
- How long does it take for data written into the dual-port to be accessible?
BULK TRANSFER Rate with CY7C68013
Can we guarantee 4 512 bytes packets per microframe data rate for bulk transfer mode through proper register settings?
