Data Retention Procedure for Async SRAM's
I am designing a battery backed up SRAM and RTC using Cypress Async SRAM (E.g. CY62128). I will use a supercap for several days of backup time. Should I pull up /CE, /WE, and /OE to VccBATT? What else should be taken into consideration?
RTC Interrupt at a Specific Time - CY8C22x45
I would like to generate an interrupt from the RTC in CY8C22x45 when the RTC's time equals a preset time. Is the RTC module in CY8C22x45 capable of generating an interrupt at a specific time? If not, how can this be implemented?
Comparision between Asynchronous and Synchronous Dual-Port RAMs
- What are the main differences between Asynchronous and Synchronous dual-port rams?
- What are the advantages and disadvantages of using either one of them?
- Under which circumstances is it better to use Async/Sync?
- Should I use asynchronous or synchronous dual-ports for my application?
- I have a fast processor. Should I use a synchronous or asynchronous dual-port?
Writing data into the dual-port
- After the data is clocked into the sync DPRAM, on which clock is the data actually written to the memory?
- How long does it take for data written into the dual-port to be accessible?