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Results 26 - 50 of 380 < Previous  3   4   5   6    ...  12   13   14   15   16   Next >
Title Customer Rating Updated
What is the Stabilitity of the PSoC ADC?

Not yet rated
08/28/09
POR and Boot routine timing

Not yet rated
08/28/09
Oscillator Frequency vs. Temperature Curve

Not yet rated
08/28/09
PSoC I/O Current Maximums

Not yet rated
08/28/09
Wake up time of CY8C20X66 family chip from sleep

Not yet rated
09/03/09
Difference between CY7C63413 and CY7C63413C

Not yet rated
09/09/09
Flash retention with E2PROM UM

Not yet rated
11/26/09
Difference between Sawn and Punch type package

Not yet rated
12/14/09
Minimum Pulse Width to Generate a GPIO Interrupt in Port Expander

Not yet rated
12/14/09
User code execution in I2CHW user module during data transfer

Not yet rated
12/14/09
POR and LVD settings are different

Not yet rated
12/17/09
POR setting based on CPU and Vdd

Not yet rated
12/17/09
Slider Diplexing in CapSense Express devices

Not yet rated
12/17/09
HSTL compliance of QDR II SRAM

Not yet rated
05/13/10
MPC680 perform burst read/writes to the PCI-DP local bus

Not yet rated
05/24/10
Boot time for CY8C20110 part

Not yet rated
06/04/10
Power-On-Reset Triggering

Not yet rated
08/30/10
Maximum sink/source current of GPIO pins on EncoreV

Not yet rated
09/26/10
Effect of increase in resolution over Noise in CapSense

Not yet rated
10/01/10
VBUS Monitoring Pin For TX2UL
Why does the TX2UL chip not have a VBUS monitoring pin?

Not yet rated
02/02/11
Part Naming conventions for HOTLink 2 parts
How are the HOTLink 2 parts named ?

Not yet rated
02/26/11
Changing the clock rate on the fly to the same port in Fullflex DPRAMs
Is it possible to change the clock rate on the fly to the same port in Fullflex DPRAMs? (For example, Is it possible to write to the memory using one clock rate, and then read from the same memory at a different clock rate to the same port?)

(4/5) by 1 user
02/26/11
GPIO Input Voltage Spec at 3.3V and 5V
What are the specified digital input voltages for the GPIOs of PSoC1, when operating at 3.3V?

Not yet rated
02/27/11
Extending the data read from an asynchronous FIFO
Is there something I can do if my processor requires a long setup and hold time to latch incoming data? How can I extend the amount of time the data is valid for? Is there a way to extend the duration of valid data on the outputs?

Not yet rated
02/28/11
Maximum tPR / tPW values for asynchronous FIFOs
Is there a maximum limit for tPR? Is there a time limit the Write strobe can be low for?

Not yet rated
02/28/11
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