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Title Customer Rating Updated
'1 /f' Noise
What is "1 / f" noise?

Not yet rated
12/26/11
2305SI-1H Moisture Sensitivity and Flammability Rating
What is the Moisture sensitivity and flammability rating of 2305SI-1H?

Not yet rated
06/23/11
230K Baud Rate Support in USB to UART Bridge Controller - KBA86260
Question: Does the USB to UART Bridge Controller support 230K baud rate?

Not yet rated
03/22/13
3.3V Tolerant inputs, with input of 2.5V on the CY2CC810
In the CY2CC810 datasheet, it states that the input is 3.3V tolerant even when operating at 2.5V, and that it does not require any external series resistors. How can this be?

Not yet rated
12/27/11
3.3V-Compatible RoboClocks
What all RoboClocks are 3.3V-compatible?

Not yet rated
11/26/13
AVCMOS Outputs of CY2CC810 Explained
Will AVCMOS outputs require terminations? Explain Operation.

Not yet rated
12/26/11
AVDD in CY22050 and CY22150 Devices
What is the AVDD power in CY22150 and CY22050 Devices and what is the current on it?

Not yet rated
09/19/11
Accuracy of switching/precharge clocks used in CSD

Not yet rated
03/13/12
Address lines driven low for the CY7C67200 in sleep mode
For the CY7C67200, when in sleep mode, the datasheet says that the address lines are driven low. Why are these inputs driven low?

Not yet rated
10/02/11
Address pin numbering in QDR II SRAMs
Why are the address lines not numbered in the pin out section of the QDR II datasheet?

Not yet rated
04/18/12
Addressing EEPROM Blocks by knowing the SRAM address only
I mistakenly overwrote the addresses of my EEPROM blocks. I can access the SRAM just fine, but not any of the EEPROM blocks. What should I do?

Not yet rated
09/19/11
Aggregate bandwidth and throughput of synchronous FIFOs
- How is the aggregate bandwidth of a synchronous FIFO calculated? - How is the aggregate throughput of a synchronous FIFO calculated?

Not yet rated
12/28/11
Air Gap between Capsense Button and Overlay Material
I have an application which as an air gap between Capsense button and Overlay Material. Are there any good solution to increase the sensitivity?

Not yet rated
11/22/13
Air Gap between Capsense Sensor and an Overlay
Can there be an air gap between a Capsense sensor and an Overlay?

Not yet rated
12/07/11
An Algorithm To Help Calculate P & Q Values
How can optimal P and Q values for the CY22393, CY22394, and CY22395 be calculated without using CyberClocks?

Not yet rated
09/17/11
Analog multiplexer in enCore III
It is mentioned in the datasheet that one can use an analog multiplexer in the enCoRe III part but I do not see a user module for the same. How to use this multiplexer?

Not yet rated
01/01/12
Arbitrary BAUD Rate of UART in PSoC 3/5
The UART datasheet of PSoC 3/5 specifies BAUD rates from 110 – 921600bps or arbitrary up to 4Mbps. What is meant by the arbitrary rate?

Not yet rated
03/23/11
Arbitration register
- How is the arbitration register used in the PCI-DP? - Does the arbitration register prevent collisions?

Not yet rated
10/11/11
Are the echo clocks CQ/CQ# differential clocks?
Are the echo clocks CQ/CQ# differential clocks?

Not yet rated
09/01/11
Are there any guidelines for CY8CLEDAC0x PCB design?
Are there any guidelines for CY8CLEDAC0x PCB design?

Not yet rated
04/12/11
Are there any guidelines for PowerPSoC PCB design?
Are there any guidelines for PowerPSoC PCB design?

Not yet rated
04/12/11
Asserting PKTEND pin when endpoint buffer is full in FX1/FX2/FX2LP
There is a note in the technical reference that states to never assert PKTEND on a full FIFO. If I have a quad buffered system and I put the last byte into the last packet, causing FULL flag to assert (operating in manual mode) can I not assert PKTEND commit the 4th packet to USB?

Not yet rated
06/19/11
Auto Tuning for Capacitive Sensors with PROC-UI - KBA82023
Question: Does PRoC-UI support auto tuning for capacitive sensors?

Not yet rated
09/27/12
BSDL model for CY37128VP84-83YMB
Is there a BSDL model available for CY37128VP84-83YMB?

Not yet rated
01/26/12
Back to Back Write in Synchronous SRAMs
Can /WE be kept LOW during back to back write or does it has to be toggle on every write on this back to back transaction in Synchronous SRAMs?

Not yet rated
09/01/11
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