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'1 /f' Noise
What is "1 / f" noise?
2305SI-1H Moisture Sensitivity and Flammability Rating
What is the Moisture sensitivity and flammability rating of 2305SI-1H?
230K Baud Rate Support in USB to UART Bridge Controller - KBA86260
Question: Does the USB to UART Bridge Controller support 230K baud rate?
3.3V Tolerant inputs, with input of 2.5V on the CY2CC810
In the CY2CC810 datasheet, it states that the input is 3.3V tolerant even when operating at 2.5V, and that it does not require any external series resistors. How can this be?
3.3V-Compatible RoboClocks
What all RoboClocks are 3.3V-compatible?
AVCMOS Outputs of CY2CC810 Explained
Will AVCMOS outputs require terminations? Explain Operation.
AVDD in CY22050 and CY22150 Devices
What is the AVDD power in CY22150 and CY22050 Devices and what is the current on it?
Accuracy of switching/precharge clocks used in CSD
Address lines driven low for the CY7C67200 in sleep mode
For the CY7C67200, when in sleep mode, the datasheet says that the address lines are driven low. Why are these inputs driven low?
Address pin numbering in QDR II SRAMs
Why are the address lines not numbered in the pin out section of the QDR II datasheet?
Aggregate bandwidth and throughput of synchronous FIFOs
- How is the aggregate bandwidth of a synchronous FIFO calculated? - How is the aggregate throughput of a synchronous FIFO calculated?
Air Gap between Capsense Button and Overlay Material
I have an application which as an air gap between Capsense button and Overlay Material. Are there any good solution to increase the sensitivity?
Air Gap between Capsense Sensor and an Overlay
Can there be an air gap between a Capsense sensor and an Overlay?
An Algorithm To Help Calculate P & Q Values
How can optimal P and Q values for the CY22393, CY22394, and CY22395 be calculated without using CyberClocks?
Analog multiplexer in enCore III
It is mentioned in the datasheet that one can use an analog multiplexer in the enCoRe III part but I do not see a user module for the same. How to use this multiplexer?
Arbitrary BAUD Rate of UART in PSoC 3/5
The UART datasheet of PSoC 3/5 specifies BAUD rates from 110 – 921600bps or arbitrary up to 4Mbps. What is meant by the arbitrary rate?
Arbitration register
- How is the arbitration register used in the PCI-DP? - Does the arbitration register prevent collisions?
Are the echo clocks CQ/CQ# differential clocks?
Are the echo clocks CQ/CQ# differential clocks?
Are there any guidelines for CY8CLEDAC0x PCB design?
Are there any guidelines for CY8CLEDAC0x PCB design?
Are there any guidelines for PowerPSoC PCB design?
Are there any guidelines for PowerPSoC PCB design?
Asserting PKTEND pin when endpoint buffer is full in FX1/FX2/FX2LP
There is a note in the technical reference that states to never assert PKTEND on a full FIFO. If I have a quad buffered system and I put the last byte into the last packet, causing FULL flag to assert (operating in manual mode) can I not assert PKTEND commit the 4th packet to USB?
Auto Tuning for Capacitive Sensors with PROC-UI - KBA82023
Question: Does PRoC-UI support auto tuning for capacitive sensors?
BSDL model for CY37128VP84-83YMB
Is there a BSDL model available for CY37128VP84-83YMB?
Back to Back Write in Synchronous SRAMs
Can /WE be kept LOW during back to back write or does it has to be toggle on every write on this back to back transaction in Synchronous SRAMs?
Bad Duty Cycle Fix Possibility by ZDB
Can a ZDB fix bad duty cycle?
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