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Title Customer Rating Updated
5V signalling support on the PCI and Local Bus interface

Not yet rated 		08/28/09
About the meaning of "Years of retention is 20 years or more"
I read from the presentation material of nvSRAM that "Years of retention is 20 years or more" in nvSRAM. Can you explain about the year of retention? Will the stored value in the NVSRAM vanish when the capacitor loses its charge?
Not yet rated 		03/26/11
Address and I/O Pin Order Flexibility for the Standard Synchronous and NoBL™ SRAMs
Address pin and I/O pin order
Not yet rated 		03/07/12
Address pin numbering in QDR II SRAMs
Why are the address lines not numbered in the pin out section of the QDR II datasheet?
Not yet rated 		04/18/12
Address pins assignments in SRAMs
What address bit is associated with each Address pin in SRAMs ? Why address pins are not numbered?
Not yet rated 		03/01/11
Advantages of Burst Modes in Single Data Rate Synchronous SRAMs- KBA80732
Question: What are the advantages of burst modes in Standard Sync/NoBL SRAMs (Single data rate synchronous SRAMs)?
Not yet rated 		06/26/12
Aggregate bandwidth and throughput of synchronous dual-ports
- How do you calculate bandwidth with dual-ports? - What is the throughput of a particular dual-port?
Not yet rated 		06/11/11
Aligning byte enables for synchronous dual port
- If I connected a 32-bit processor to a 36-bit wide dual-port, how can I align the byte enables? - Can I use the byte enables of the 18-bit wide dual-port if my system is only 16 bits?
Not yet rated 		06/11/11
Arbitration code for Dual port SRAMs when accessed from both sides
- Since there is no guarantee as to what data is read during simulatneous access, can I control that with logic? - Do you have anything to help prevent corrupting of data when trying to write to the same location at the same time?
Not yet rated 		03/27/11
Are the echo clocks CQ/CQ# differential clocks?
Are the echo clocks CQ/CQ# differential clocks?
Not yet rated 		09/01/11
Async SRAM's support BSDM format models (Boundary Scan Description Model)?
Does Async SRAM's support BSDM format models (Boundary Scan Description Model)?
Not yet rated 		06/26/11
Asynchronous Address Glitch During Write Cycle
Is it acceptable for the address to change during the write cycle?
Not yet rated 		03/24/11
Asynchronous vs Synchronous(Clocked) FIFOs
- What is the difference between clocked and synchronous FIFO's? - What different types of FIFO's are there? - Why should one prefer one type over another?
Not yet rated 		06/13/11
BHE\ and BLE\ pins of a x16 part
I want to access 16 bit data at a time from SRAM of a x16 part, how should I connect BHE\ and BLE\ pins?
Not yet rated 		03/24/11
BUSY signals when cascading asynchronous dual-ports
How should I use the BUSY signal in width expansion mode? Why are there BUSY inputs and BUSY outputs? Why is there a Master and a Slave dual-port? Why would I need a slave dual-port?
Not yet rated 		03/26/11
Back to Back Write in Synchronous SRAMs
Can /WE be kept LOW during back to back write or does it has to be toggle on every write on this back to back transaction in Synchronous SRAMs?
Not yet rated 		09/01/11
Back to Back Write in Synchronous SRAMs - KBA82781
Question: Can /WE be kept LOW during back-to-back write or does it has to be toggle on every write on this back-to-back transaction in Synchronous SRAMs?
Not yet rated 		10/03/12
Battery Backup memory interface

Not yet rated 		08/28/09
Battery back up for SRAM's
Does Cypress recommend any lithium battery backup for SRAM's?
Not yet rated 		03/13/12
Battery backed solutions for CY7C08xxV dual-ports
Why is the standby current rating (Isb) on these 2Mb (CY7C0851V) and 4Mb (CY7C0852V) dual-ports so high compared to the 1Mb devices? I would expect the difference in Isb to be fairly linear, but it is, in fact, several orders of magnitude greater. (10 mA vs. 10-50uA). The complication comes in looking for a battery backup switcher. I've found none of these power monitors can handle >150uA of standby current. Does Cypress have an battery backed solution available for these high-density dual-ports?
Not yet rated 		06/11/11
Benefits of NVSRAM over BBSRAM
What are the benefits of NVSRAM over BBSRAM ?
Not yet rated 		03/26/11
Benefits of NVSRAM over EEPROM
What are the benefits of NVSRAM over EEPROM ?
Not yet rated 		03/26/11
Benefits of NVSRAM over Flash Memory
What are the benefits of NVSRAM over Flash Memory ?
Not yet rated 		03/26/11
Benefits of NVSRAM over Low-Power Asynchronous SRAM
What are the benefits of NVSRAM over Low-Power Asynchronous SRAM ?
Not yet rated 		03/26/11
Burst Counter Operation and chip disabled for synchronous dual port SRAM's
If I do a read or write of a number of words and I use the internal counter (ie load the counter start address on the first word and then count after that), but I only give a CE (chip enable) every other clock; will I read data from consecutive address locations every other clock? An example: For a burst read -- first clock load counter, second clock do nothing, third clock give chip enable and read first data, fourth clock do nothing, fifth clock give chip enable and read second data (next one in memory after first), sixth clock do nothing, seventh clock give chip enable and read third data, etc. Note that output enable and counter enable will always be active. Could you confirm this for me?
(5/5) by 1 user 		06/11/11
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