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Title Customer Rating Updated
Burst Counter Operation and chip disabled for synchronous dual port SRAM's
If I do a read or write of a number of words and I use the internal counter (ie load the counter start address on the first word and then count after that), but I only give a CE (chip enable) every other clock; will I read data from consecutive address locations every other clock? An example: For a burst read -- first clock load counter, second clock do nothing, third clock give chip enable and read first data, fourth clock do nothing, fifth clock give chip enable and read second data (next one in memory after first), sixth clock do nothing, seventh clock give chip enable and read third data, etc. Note that output enable and counter enable will always be active. Could you confirm this for me?
(5/5) by 1 user 		06/11/11
Data Valid Window Calculation
How do you calculate the Data Valid Window in QDRII SRAMs?
(5/5) by 1 user 		09/01/11
Depth and width expansion affect on board-level timing
How does memory depth and width expansion affect board-level timing?
(5/5) by 1 user 		06/11/11
Flow-through vs. Pipelined memory
- What is the difference between FT and PL modes? - Which mode should I use? - Why are newer dual-ports pipelined only?
Not yet rated 		03/27/11
IO power in SRAMs
Does the datasheet provide sum of core power and IO power? How do I calculate the IO power in SRAMs?
(5/5) by 1 user 		02/26/11
NC and DNU pin
What is NC and DNU pin and what should I do with them, please suggest?
(5/5) by 1 user 		03/01/11
NoBL Sram Definition
What is a NoBL SRAM?
(5/5) by 1 user 		06/18/11
Part Number Decoder for Cypress NoBL SRAMs
Where can I find Part Number Decoder for NoBL SRAMs ?
(5/5) by 1 user 		01/01/12
Part Number Decoder for Standard Sync SRAMs
Where can I find Part Number Decoder for Standard Sync SRAMs?
(5/5) by 1 user 		09/01/11
Power up sequence and the use of DOFF# in QDRII/II+ and DDRII/II+ SRAMs
What is the power up and initialization sequence to be followed for the QDRII/II+ and DDRII/II+ devices?
Not yet rated 		09/01/11
Subsystem Device ID and Vendor ID

Not yet rated 		08/28/09
Time taken for Software Store and Hardware Store
What is the difference in time taken for Software and Hardware Store?
Not yet rated 		03/30/11
Usage of the Output Enable (OE) Signal in Synchronous FIFOs
1. If OE is high, what happens to the data bus? 2. If there is a valid read operation, but OE is high, will the next read operation be the same word or the following word in the FIFO? 3. If OE is high during reset, will the data bus remain in a high-Z state? 4. Is it okay to connect the OE pin to ground?
Not yet rated 		06/17/11
Vss and Vcc clarification
Which pin is ground: Vcc or Vss?
Not yet rated 		03/13/12
nvSRAM SEL and SER Data
Explain SEL and SER for Cypress NVSRAM's
Not yet rated 		03/30/11
Part Number Decoder for Fast Asynchronous SRAMs
Is a Part number decoder available for the Cypress Fast Async SRAMs?
(4.5/5) by 2 users 		02/26/11
Maximum Junction Temperature and Power Consumption Calculator
How can I find the power consumption, maximum junction temperature and absolute maximum temperature of an SRAM part ?
(4/5) by 1 user 		05/07/12
NOP cycles in Sync SRAMs
When is a second NOP cycle required in Sync SRAM?
(5/5) by 1 user 		02/27/11
Address pins assignments in SRAMs
What address bit is associated with each Address pin in SRAMs ? Why address pins are not numbered?
Not yet rated 		03/01/11
BHE\ and BLE\ pins of a x16 part
I want to access 16 bit data at a time from SRAM of a x16 part, how should I connect BHE\ and BLE\ pins?
Not yet rated 		03/24/11
Changing the clock rate on the fly to the same port in Fullflex DPRAMs
Is it possible to change the clock rate on the fly to the same port in Fullflex DPRAMs? (For example, Is it possible to write to the memory using one clock rate, and then read from the same memory at a different clock rate to the same port?)
(4/5) by 1 user 		02/26/11
Cypress FIFO Architecture
- How is the FIFO made? - Is the FIFO memory volatile or non-volatile? - Is the FIFO memory static or dynamic? - What is the architecture of Cypress FIFOs? - Are Cypress FIFOs bubble-through FIFOs?
Not yet rated 		06/13/11
Difference between CY14B101L and Simtek part STK14CA8
What is difference between CY14B101L and Simtek part STK14CA8 ?
(5/5) by 1 user 		03/27/11
I/O Switching Power for Sync SRAM - KBA82208
Question: Is the IDD (VDD operating supply current) current specified in the Sync SRAM datasheets sum of both the core current and I/O current?
(4/5) by 1 user 		10/18/12
Is there a device equivalent CYPRESS parts for DS1315 (Real Time Clock chip) and DS1212Q (Non-Volatile Controller for SRAM)?
Is there a device equivalent CYPRESS parts for DS1315 (Real Time Clock chip) and DS1212Q (Non-Volatile Controller for SRAM)?
Not yet rated 		03/26/11
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