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Title	Customer Rating	Updated
Difference between parity bits and regular data I/O lines Some of the cypress synchronous devices have parity pins. Are these same as regular I/O pins?	Not yet rated	03/30/11
Writing data into the dual-port - After the data is clocked into the sync DPRAM, on which clock is the data actually written to the memory? - How long does it take for data written into the dual-port to be accessible?	Not yet rated	03/27/11
Read data problems in synchronous dual-ports Why is the data read from a synchronous dual-port always the last word written even though the read address is different than the write address?	Not yet rated	03/27/11
Generation of FIFO empty and full flags How are FIFO empty and full flags generated?	Not yet rated	03/27/11
Pulling multiple I/Os to Vcc through only 1 pull up resistor Is it fine to pull up (or down) multiple signals through only 1 resistor?	Not yet rated	03/27/11
Unused I/Os for Dual port SRAM's - What should I do with the unused I/O pins? - Can unused I/Os be tied to each other if the relevent byte enable is disabled? - What should I do if my processor is only 32 bits wide and the data bus is 36 bits wide?	(4/5) by 1 user	03/27/11
Creating a FIFO using a synchronous burst dual-port RAM - Can I use a dual-port as a FIFO? - If I am using the burst mode of a dual-port to create a FIFO, what should I do with the address lines?	Not yet rated	03/27/11
Clearing the mailbox interrupt - How to clear the interrupt signal ? - How to use the mailbox feature? - What is min value of time when an interrupt is observed to the time when the interrupt is cleared?	Not yet rated	03/27/11
Output Enable (OE) signal behavior Is OE# an asynchronous or synchronous input?	Not yet rated	03/27/11
Flow-through vs. Pipelined memory - What is the difference between FT and PL modes? - Which mode should I use? - Why are newer dual-ports pipelined only?	Not yet rated	03/27/11
Arbitration code for Dual port SRAMs when accessed from both sides - Since there is no guarantee as to what data is read during simulatneous access, can I control that with logic? - Do you have anything to help prevent corrupting of data when trying to write to the same location at the same time?	Not yet rated	03/27/11
Difference between CY14B101L and Simtek part STK14CA8 What is difference between CY14B101L and Simtek part STK14CA8 ?	(5/5) by 1 user	03/27/11
Replacing a CY7C14X slave device with a CY7C13X master device For a Dual port SRAM, Can I replace a slave device with a master device? What are the differences between the slave devices and master devices? - Can I use only master devices?	Not yet rated	03/27/11
Replacing obsolete asynchronous dual-port RAMs The part I was using is now obsolete. What is a good replacement part? Is there something I can use to replace this asynchronous dual-port? What is important when picking a replacement asynchronous dual-port?	Not yet rated	03/27/11
Write Operation Timing of Asynchronous Dual-ports - When is the internal logic of an asynchronous dual-port latch the address during a write cycle? - Is the address latched when CE# transitions to low? - Do write operations begin when R/W# transitions to low or when CE# and R/W# both transition to low?	Not yet rated	03/27/11
Comparision between Asynchronous and Synchronous Dual-Port RAMs - What are the main differences between Asynchronous and Synchronous dual-port rams? - What are the advantages and disadvantages of using either one of them? - Under which circumstances is it better to use Async/Sync? - Should I use asynchronous or synchronous dual-ports for my application? - I have a fast processor. Should I use a synchronous or asynchronous dual-port?	Not yet rated	03/27/11
Mailbox memory location arbitration for dual port RAMs How is simultaneous access of the mailbox locations handled? What happens if I read and write from the same mailbox at the same time?	Not yet rated	03/26/11
MoBL DP - Power down feature of MoBL with the control pin configuration Can the MoBL dual port be powered down? What are the features and pin configuration if such a condition can exist?	Not yet rated	03/26/11
Pb-Free option of SRAMs What are the differences in reflow/assembly process required by Pb-Free devices?	Not yet rated	03/26/11
Simultaneous access arbitration in asynchronous dual-ports - What happens if I try to access the same memory location from both ports at the same time? - If I read from one port and write from another at the same time, what data will be read out? - What happens if I write to the same address from both ports?	Not yet rated	03/26/11
BUSY signals when cascading asynchronous dual-ports How should I use the BUSY signal in width expansion mode? Why are there BUSY inputs and BUSY outputs? Why is there a Master and a Slave dual-port? Why would I need a slave dual-port?	Not yet rated	03/26/11
CY7C138AV / 144AV / 006AV / 007AV / 139AV / 145AV / 016AV / 017AV Interrupt output type for Asynchronous Dual port RAM's What kind of outputs are INTL and INTR in CY7C006AV? E.g Are the interrupts of CY7C145AV open drain? Can I tie INTL and INTR together?	Not yet rated	03/26/11
Differences between 'V' parts and 'non-V' asynchronous dual-port RAMs What is the difference between CY7Cxxxx and CY7CxxxxV for asynchronous dual-port RAMs? Why do some part numbers have a V in the end?	Not yet rated	03/26/11
SRAM KGD How can the SRAM KGD be Obtained?	Not yet rated	03/26/11
Glitch on power supply line during recall How does Power up Recall operation work when VCC is non-monotonic during power up?	Not yet rated	03/26/11

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