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Title	Customer Rating	Updated
Usage of XI#, XO#, and FL#/RT signals - What should pin XOn, /XO, RXOn, /RXO, RXIn, /RXI, WXOn, /WXO, WXIn, /WXI, FLn, /FL be tied to if I am not cascading? - What should these pins be tied to if I am width cascading? - What should these pins be tied to if I am depth cascading?	Not yet rated	06/17/11
Maximum number of cascaded FIFOs How many FIFOs can I cascade in depth and by width? What are the considerations?	Not yet rated	06/17/11
Using a FIFO as a transparent device - Can the FIFO be used transparently? - Can data written into the FIFO be read straight out? - Can one tie WCLK and RCLK together?	Not yet rated	06/17/11
Asynchronous vs Synchronous(Clocked) FIFOs - What is the difference between clocked and synchronous FIFO's? - What different types of FIFO's are there? - Why should one prefer one type over another?	Not yet rated	06/13/11
Signal Overshoot / Undershoot - How does signal overshoot affect FIFO operation? - How does one fix overshoot/undershoot problems on the board?	Not yet rated	06/13/11
Cypress FIFO Architecture - How is the FIFO made? - Is the FIFO memory volatile or non-volatile? - Is the FIFO memory static or dynamic? - What is the architecture of Cypress FIFOs? - Are Cypress FIFOs bubble-through FIFOs?	Not yet rated	06/13/11
General FIFO - Tri-stated signal connected to data inputs What will happen if we have a tri-state output connected to the input of the FIFO? We are always driving the clock and control inputs; it is only the data inputs that will be receiving a tri-stated floating signal.	Not yet rated	06/13/11
External Master Reset of all Cypress FIFO's - Is there a built-in reset in Cypress FIFO's? - Is there POR circuitry in Cypress FIFO's? - Do I need to reset the FIFO on power up?	Not yet rated	06/13/11
Master Reset problems - What all things can affect Master Reset? - Even after following timing specifications for Master Reset, it is not working , why ? - Will noise on the signal lines affect the functionality of the device.	Not yet rated	06/13/11
Unidirectional vs. Bidirectional FIFOs What is the difference between unidirectional and bidirectional FIFO's? Why would I use a bidirectional FIFO? How is memory shared in a bidirectional FIFO?	Not yet rated	06/13/11
Using /FF as a Half Full flag in depth cascaded FIFO's If cascading two FIFO's in depth, can the full flag (/FF) of the first FIFO be used as the half full flag for both FIFO's?	Not yet rated	06/13/11
Replacing asynchronous FIFO's with synchronous FIFO's - What design considerations are there when converting from an asynchronous FIFO to a synchronous one? - What is different about designing with synchronous FIFOs? - Can you operate a synchronous FIFO as an asynchronous one?	Not yet rated	06/13/11
FIFOs vs Dual-ports When is a FIFO used instead of a dual port? How do I select between a FIFO and dual-port for my application?	(3/5) by 1 user	06/11/11
Aggregate bandwidth and throughput of synchronous dual-ports - How do you calculate bandwidth with dual-ports? - What is the throughput of a particular dual-port?	Not yet rated	06/11/11
Using multiple devices to create a wider data path for synchronous dual port SRAM's How can multiple dual-port devices be combined to create a wider data path? Can I width cascade multiple dual-ports? How would I set up the dual-port for width expansion?	Not yet rated	06/11/11
Depth and width expansion affect on board-level timing How does memory depth and width expansion affect board-level timing?	(5/5) by 1 user	06/11/11
CY7C08xxV Read Cycle Latency - Why is there no FT/PL pin in some of the synchronous dual-ports? - What is the latency associated with read operations?	Not yet rated	06/11/11
Battery backed solutions for CY7C08xxV dual-ports Why is the standby current rating (Isb) on these 2Mb (CY7C0851V) and 4Mb (CY7C0852V) dual-ports so high compared to the 1Mb devices? I would expect the difference in Isb to be fairly linear, but it is, in fact, several orders of magnitude greater. (10 mA vs. 10-50uA). The complication comes in looking for a battery backup switcher. I've found none of these power monitors can handle >150uA of standby current. Does Cypress have an battery backed solution available for these high-density dual-ports?	Not yet rated	06/11/11
Simultaneous access in synchronous dual-ports - Can I write to the dual-port at the same time from both ports? - What happens when I read and write to the same location at the same time? - What happens if I read from the same location at the same time? - If both ports are running off the same clock how may clock cycles after I write can I initiate a read from the same address?	(4/5) by 1 user	06/11/11
Read-Back of Internal Address Counters for synchronous dual port SRAM's - How can one see the current state of the internal counter? - Is there a way to check the state the burst counter? - Is address readback different for the CY7C08x1V / CY7C08x2V devices?	Not yet rated	06/11/11
Unused OE# and CE1 Pins If I am not going to use these pins, what should I do with them?	Not yet rated	06/11/11
VSS vs. VSSQ for synchronous dual port SRAM's What is the difference between VSSQ versus VSS in the datasheet?	Not yet rated	06/11/11
Burst Counter Operation and chip disabled for synchronous dual port SRAM's If I do a read or write of a number of words and I use the internal counter (ie load the counter start address on the first word and then count after that), but I only give a CE (chip enable) every other clock; will I read data from consecutive address locations every other clock? An example: For a burst read -- first clock load counter, second clock do nothing, third clock give chip enable and read first data, fourth clock do nothing, fifth clock give chip enable and read second data (next one in memory after first), sixth clock do nothing, seventh clock give chip enable and read third data, etc. Note that output enable and counter enable will always be active. Could you confirm this for me?	(5/5) by 1 user	06/11/11
Read and Write with Single Internal Counter for Synchronous Dual port SRAM's What happens if we write on one clock cycle with ADS#, CE# and CNTEN# all low (i.e. load the address counter) and then, on the next cycle we read without ADS# but with CNTEN# (i.e. increment the counter). Will the address we read from be one higher than the one we loaded in the first cycle?	Not yet rated	06/11/11
Timing relationship of OE# to the dual-port What is the timing relationship between OE# and CE# in synchronous Dual Ports? - How is the output enable signal connected to the clocks?	Not yet rated	06/11/11

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