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Title Customer Rating Updated
NoBL SRAM CY7C1370DV25 JTAG test
The NoBL SRAM CY7C1370DV25 issue list indicates that the part does not support boundary scan. Can I still run the boundary scan / JTAG test on a system which has this memory?
Not yet rated 		06/18/11
Termination design on the Sync SRAM NoBL
What is the recommendation for the termination design for the Standard Synchronous/ NoBL SRAMs ?
Not yet rated 		06/18/11
Number of cycles required to read CY7C1380 (standard Sync pipeline)
Is it possible to do an ARBITRARY NUMBER of CONSECUTIVE read access (one access per clock cycle) to a series of random locations; i.e. it is possible to use this chip to read the entire memory in 512K clock cycles?
Not yet rated 		06/18/11
Parity generation during Read and Write
How is parity generated during reads and write?
(4/5) by 1 user 		06/18/11
TDO Output of the JTAG circuitry
When Boundary Scan input signals are applied to TDI, TCK and TMS pins of the chip, no output signal can be detected from TDO pin of the chip. What is the problem?
Not yet rated 		06/18/11
Clock enable CEN# reduces power consumption if disabled
Does Clock enable CEN# reduce power consumption if disabled (High)?
Not yet rated 		06/18/11
SRAM load Conditions for given specs
What is the load to which the datasheet parameters are guaranteed for?
Not yet rated 		06/18/11
necessity of clock when a ZZ pin is asserted
According to the datasheet for a Sync SRAM device, the clock is still available to the device after the asynchronous ZZ signal is asserted. Is the clock necessary? Is it possible to stop applying the clock, by tying the clock to either "1" or "0", after asserting the ZZ signal?
Not yet rated 		06/18/11
SRAM Interface to Motorola 7410 Processor
What are the ranges of densities that can be used for L2 Cache application with a Motorola 7410 Processor?
Not yet rated 		06/18/11
NoBL Burst and Standard NoBL differences
What are the differences between the standard NoBL and the NoBL Burst 72M SRAMs?
Not yet rated 		06/18/11
NoBL Sram Definition
What is a NoBL SRAM?
(5/5) by 1 user 		06/18/11
Package selection of Synch SRAMs
What are the selection criteria in selecting a package for Synchronous SRAMs?
Not yet rated 		06/18/11
Sync Burst SRAM Deselect Sequence
How do we deselect a Sync Burst SRAM?
Not yet rated 		06/18/11
Use of ADV/LD pin
What is the use and the function of the ADV/LD pin?
Not yet rated 		06/18/11
Read / Write control signals on unidirectional FIFOs
Why is there a read/write control signal (R/W#) on each port for a unidirectional FIFO?
Not yet rated 		06/18/11
Writing at the Full Boundary
- What happens if FIFO is continuously write into when Full Flag is asserted? - My system is set up to continuously write until the FIFO is full. Once it is full, I begin to read out the data. However, it seems like I lose some of the data being written into the FIFO when I do so. RCLK and WCLK are the same. What is wrong?
Not yet rated 		06/17/11
Usage of the Output Enable (OE) Signal in Synchronous FIFOs
1. If OE is high, what happens to the data bus? 2. If there is a valid read operation, but OE is high, will the next read operation be the same word or the following word in the FIFO? 3. If OE is high during reset, will the data bus remain in a high-Z state? 4. Is it okay to connect the OE pin to ground?
Not yet rated 		06/17/11
Synchronous FIFO architecture
What is the architecture of the Synchronous FIFOs? Is the memory managed by pointers or shifting registers? If the fullness of the FIFO is managed well, is it possible to endlessly read and write?
Not yet rated 		06/17/11
Usage of different speed grades in synchronous FIFOs
- Can I replace a -35 device with with a -25 device? - If the two ports of my FIFO are running at different rates, how do I pick a speed grade for my system?
Not yet rated 		06/17/11
Driving REN1 and REN2 together for some families of synchronous FIFO's
- Can I drive /REN1 and /REN2 with the same signal? - Can I tie Read Enable 1 and Read Enable 2 together?
Not yet rated 		06/17/11
Retransmit feature of synchronous FIFO's
- What happens to the data lines when RT is pulsed and during the tRTR time? - Can a selected block of data be retransmitted? - What considerations are there for using the retransmit operation?
Not yet rated 		06/17/11
Delay buffers using synchronous FIFOs
How can I make a delay buffer that always has x number of words in the buffer?
Not yet rated 		06/17/11
Synchronous FIFO Clocks
- Are there any requirements for clock duty cycles? - Do the clocks have to have 50 percent duty cycles? - What are the requirements for the clock driving sync FIFOs?
Not yet rated 		06/17/11
Output State for the FIFOs
- Can I make the data outputs (Q0 - Q8) to be normally high? - What is the status of the data outputs after reset? - What happens to the data outputs when /OE is asserted?
Not yet rated 		06/17/11
Driving 3.3V I/Os on a 5V device
- Can I drive 3.3V I/Os into a 5V part? - What are the minimum input levels for 5V devices? - Will my 3.3V processor be strong enough to connect to a 5V device? - Will a -1V undershoot on the inputs cause problems?
Not yet rated 		06/17/11
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