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Title	Customer Rating	Updated
Events causing Soft Error Rate (SER) in Sync SRAMs What are the various events causing Soft Error Rate (SER) in Sync SRAMs?	Not yet rated	09/01/11
QDRII/DDRII/QDRII+/DDRII+ clocking How should be QDRII/DDRII/QDRII+/DDRII+ clocking ?	Not yet rated	09/01/11
Part Number Decoder for Standard Sync SRAMs Where can I find Part Number Decoder for Standard Sync SRAMs?	(5/5) by 1 user	09/01/11
nvSRAM operation at ambient temperature beyond value specified in datasheet Can an industrial temperature range nvSRAM part be used in applications where the ambient temperature occasionally exceeds 85C?	Not yet rated	07/29/11
Pull up value of "MODE" pin on CY7C1360C What is the value of pull up resistance on the "MODE" pin on CY7C1360C?	Not yet rated	07/01/11
Semaphore Value in Asynchronous Dual-Ports - What are the uses of Semaphore latches? - How are semaphore values read on the I/O bus?	Not yet rated	06/27/11
Synchronous FIFO Flag Update Cycle - What is the Flag Update Cycle? - Must the FIFO be read to update the empty flag? - Must the FIFO be written to for the full flag to be updated?	Not yet rated	06/27/11
Usage of the Vcc/SMODE# pin	Not yet rated	06/27/11
Does CY62256 have pull up resistor on the I/O ? Does this part have pull up resistors on the I/O pins?	Not yet rated	06/26/11
Overshoot and Undershoot spec in datasheet What are the overshoot and undershoot specs of Async SRAM's	Not yet rated	06/26/11
Async SRAM's support BSDM format models (Boundary Scan Description Model)? Does Async SRAM's support BSDM format models (Boundary Scan Description Model)?	Not yet rated	06/26/11
Decoupling for the CY7C1041CV33-12BAI ? What decoupling scheme should I use for Async SRAM's?	(1/5) by 1 user	06/26/11
Data retention mode for the CY7C1049CV33 ? What is the difference between stand-by mode and data retention mode for the CY7C1049CV33?	Not yet rated	06/26/11
cross-section drawings and thickness ? Where do I Request a cross-section drawing with layers labeled and nominal thickness that can be identified?	Not yet rated	06/26/11
Termination guidelines for interfacing QDR II SRAMs with Virtex FPGAs Do you recommend any specific termination guidelines for interfacing QDR II SRAMs with Virtex FPGAs?	Not yet rated	06/24/11
Master Reset cycle - How to reset the FIFO? - How to operate /MR? - What is a proper reset?	Not yet rated	06/23/11
DIFFERENCE BETWEEN THE CY62128LL-70SC AND CY62128BLL-70SC ? What is the difference between the CY62128LL-70SC AND CY62128BLL-70SC ?	Not yet rated	06/20/11
SRAM Environmental Testing Where is the environmental and mechanical testing data available.	Not yet rated	06/20/11
Burst and NoBL SRAM access What do you mean by 2-1-1-1 and 3-1-1-1 accesses which you show for Sync Burst and NoBL SRAMs?	Not yet rated	06/18/11
Simultaneous Reads and Writes on the CY7C1302 QDR On the QDR SRAM, can I give a READ and WRITE command simultaneously?	Not yet rated	06/18/11
JTAG pins floating If we do not want to use the JTAG, can we leave those pins floating?	Not yet rated	06/18/11
Capturing data with a single clock using DDR SRAMs I am using a FPGA with a DDR interface that will support capturing data off both edges of a single clock. Can I use only one of the CQ and CQ* pairs and capture both edges?	Not yet rated	06/18/11
Effect of Speed, Package Type and Die Revisions on Models When browsing the website for SRAM models, I have noticed that certain speeds have the same models while other models are package or revision specific. How do you know which models are affected by revisions, packages, or speed of the device.	Not yet rated	06/18/11
K and K\ signals in DDR Are K, K\ are differential signals in DDR?	Not yet rated	06/18/11
Standby current when address lines are float Does floating address lines in the standby mode have any effect on the standby current of the device?	Not yet rated	06/18/11

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