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Title	Customer Rating	Updated
An error occurred while trying to download package information I am facing following problem while downloading PSoC Designer. Error message:- "An error occurred while trying to download package information"	Not yet rated	12/05/10
Are the FIFO's accessible (for either reads or writes) when the part enters BIST mode (CY7C924ADX or CY7C9689A) 1)Can I read characters from the RXFIFO during BIST mode (CY7C924ADX or CY7C9689A)? 2)Can I write characters to the TXFIFO during BIST mode (CY7C924ADX or CY7C9689A)?	Not yet rated	07/01/11
Are the receiver discard policies affected when the FIFO's are bypassed in the CY7C924ADX? Are the receiver discard policies affected when the FIFO's are bypassed in the CY7C924ADX?	Not yet rated	06/10/11
Avoiding overflow of RX FIFO in the CY7C924ADX and CY7C9689A. How to avoid RX FIFO overflow in the CY7C924ADX and CY7C9689A?	Not yet rated	12/07/11
Board modifications to potentially improve the powerline communication performance of the low-voltage PLC boards (CY3273, CY3275) Are there any board modifications that I can make to the low-voltage PLC boards (CY3273, CY3275) to improve powerline communication performance?	Not yet rated	09/01/11
Built-In Selt-Test (BIST) and why should I use it? What is Built-In Selt-Test (BIST) and why should I use it?	Not yet rated	06/13/11
C3ISR programming Cable - Supported devices	Not yet rated	12/08/09
CKR outputs are unusable when the serial inputs to the CY7B933 are left floating and a REFCLK of 40MHz is supplied. When the serial inputs to the CY7B933 are left floating and REFCLK of 40MHz is supplied,Why are CKR outputs are unusable?	Not yet rated	06/24/11
CY9266 Evaluation Board documentation 1)How do I test the CY9266 evaluation board? 2)What types of evaluation boards are available for testing the CY7B923/CY7B933? 3)How do I setup BIST on the CY9266 evaluation board?	Not yet rated	06/27/11
CYP15G0403DXB BGA Pad Opening Details	Not yet rated	11/13/09
Can the FIFO be bypassed in CY7C924ADX when using the byte-packer Can I bypass the FIFO in CY7C924ADX when I want to use 10-bit encoded mode?	Not yet rated	07/01/11
Channel bonding: Elasticity buffer behavior in channel bonded mode	Not yet rated	03/08/10
Character Rate vs Byte Rate Explanation of what character rate vs byte rate means?	Not yet rated	06/13/11
Characteristics and considerations for HOTLink jitter What are the characteristics and considerations for HOTLink jitter?	Not yet rated	12/07/11
Configuration for connecting the HOTLink Transmitter/Receiver power and ground pins What is the optimum configuration for connecting the HOTLink Transmitter/Receiver power and ground pins?	Not yet rated	06/13/11
Configuration of the Status In (SI) and Status Out (SO) Pins 1) If I want to use the SO pin as a true output of SI, but the signal it is connected to is pulled up to Vcc during startup, will this affect the configuration of SO? 2) Can I change the state of SO is used during operation? 3) How is the function of the INB(INB+) input and the SI(INB-) input defined?	Not yet rated	07/01/11
Configure the HOTLink 1 for 3.3V I/O? Is there a way to configure the HOTLink 1 for 3.3V I/O?	Not yet rated	07/01/11
Considerations in Interfacing HOTLink II to Fiber Optic Module What are the considerations in Interfacing HOTLink II to Fiber Optic Module? How can I interface a SFP fiber optic module with HOTLink II?	Not yet rated	06/13/11
Country of Origin (COO) Information Where can I find the Country of Origin (COO) of a Cypress product?	Not yet rated	05/24/12
Cypress Parts Baking Condition Information Do Cypress parts require baking? If so, what are the conditions?	Not yet rated	05/24/12
Cypress' Parts Shelf Life Condition Information What is Cypress’s Parts Shelf Life condition?	Not yet rated	04/19/12
Data stream is always valid when RVS is LOW Is it guaranteed that the data stream is always valid when RVS is LOW?	Not yet rated	12/07/11
HOTLink DX PECL Output to LVTTL Input - How do I connect the differential PECL outputs of the CY7C924ADX or CY7C9689A to a single-ended LVTTL input? - Is it possible to use a LVTTL optical module? - How do I make a PECL to LVTTL translation?	Not yet rated	02/03/11
HOTLink II Three Level Control Inputs Can the 3-Level select static control inputs be controlled by an FPGA/CPLD output? (For CYP(V)15G0401DXB, CYP(V)15G0402DXB, CYP(V)15G0201DXB, and CYP(V)15G0101DXB).	Not yet rated	06/13/11
IBIS/SPICE models for the CY7B923/933 Are there IBIS/SPICE models for the CY7B923/933?	Not yet rated	02/03/11

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