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Title	Customer Rating	Updated
CY9266 Evaluation Board documentation 1)How do I test the CY9266 evaluation board? 2)What types of evaluation boards are available for testing the CY7B923/CY7B933? 3)How do I setup BIST on the CY9266 evaluation board?	Not yet rated	06/27/11
Meaning in datasheet, when it says that you can write to the FIFO from DC to 50 MHz What does the datasheet mean when it says that you can write to the FIFO from DC to 50 MHz?	Not yet rated	06/24/11
Reducing Power Dissipation: Unused serial outputs on CY7C9689 What do I do with the unused serial outputs OUTA±/OUTB± on the CY7C9689 device? Is there a setting that is particularly beneficial?	Not yet rated	06/24/11
Transformers recommendation for HOTLink CY7B9234 and CY7B9334 What transformers does Cypress recommend for HOTLink CY7B9234 and CY7B9334?	Not yet rated	06/24/11
Latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver. What is the latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver?	Not yet rated	06/24/11
Rad hardness, Soft Error Rate (SER), Single Event Upset (SEU) rates for the CY7B923 and CY7B933. What information do you have about rad hardness, Soft Error Rate (SER), Single Event Upset (SEU) rates for the CY7B923 and CY7B933?	Not yet rated	06/24/11
CKR outputs are unusable when the serial inputs to the CY7B933 are left floating and a REFCLK of 40MHz is supplied. When the serial inputs to the CY7B933 are left floating and REFCLK of 40MHz is supplied,Why are CKR outputs are unusable?	Not yet rated	06/24/11
SPDSEL and RANGESEL for 100MBaud (CY7C9689A, CY7C924ADX) 1) What would be the setting on the SPDSEL and RANGESEL, if the chip has to be operated at 100 MBaud? The speed may vary above or below 100 Mbaud and Refclk would be 20 MHz? 2) -Do you recommend a spread sprectrum clock?	Not yet rated	06/22/11
HOTLink II Three Level Control Inputs Can the 3-Level select static control inputs be controlled by an FPGA/CPLD output? (For CYP(V)15G0401DXB, CYP(V)15G0402DXB, CYP(V)15G0201DXB, and CYP(V)15G0101DXB).	Not yet rated	06/13/11
Switching between Serial Differential Inputs - How long does it take for HOTLInk II receiver to switch between the serial differential inputs from IN1(+/-) to IN2(+/-) - How long does it take for HOTLInk II receiver to switch between the serial differential inputs from IN1(+/-) to IN2(+/-) - IN1(+/-) is coming from an external link. OUT2(+/-) loop back's to IN2(+/-). Two channels have the same freq. Before the external link is established, we select IN2. We have plenty of time for the receiver to lock in IN2. When the external link on IN1 becomes OK, we switch the receiver to IN1. How long does it take for the clock recovery to lock in? Does it still take 376K UI?	Not yet rated	06/13/11
Considerations in Interfacing HOTLink II to Fiber Optic Module What are the considerations in Interfacing HOTLink II to Fiber Optic Module? How can I interface a SFP fiber optic module with HOTLink II?	Not yet rated	06/13/11
Receive Status Bits in HOTLink II What is the purpose of receive status bits in HOTLink II? What is the function of priority in table 20 of the data sheet of CYP15G0401DXB? What are the different modes of status reporting?	Not yet rated	06/13/11
State of the RXSC/D* signal while VLTN is asserted for the CY7C9689A What is the state of the RXSC/D* signal while VLTN is asserted for the CY7C9689A?	Not yet rated	06/13/11
Significance of HOTLink claim of requiring no external PLL components? What is the significance of the HOTLink claim of requiring no external PLL components?	Not yet rated	06/13/11
Power consumption of the SMPTE 259M Scrambler/Controller and Descrambler/Framer-Controller What is the typical power consumption of the SMPTE 259M Scrambler/Controller and Descrambler/Framer-Controller?	Not yet rated	06/13/11
Power (VDDA & VDD) and ground (VSSA & VSS) pins on the CY7C924ADX What needs to be done with the power (VDDA & VDD) and ground (VSSA & VSS) pins on the CY7C924ADX?	Not yet rated	06/13/11
Configuration for connecting the HOTLink Transmitter/Receiver power and ground pins What is the optimum configuration for connecting the HOTLink Transmitter/Receiver power and ground pins?	Not yet rated	06/13/11
Character Rate vs Byte Rate Explanation of what character rate vs byte rate means?	Not yet rated	06/13/11
Built-In Selt-Test (BIST) and why should I use it? What is Built-In Selt-Test (BIST) and why should I use it?	Not yet rated	06/13/11
Power supply decoupling required for HOTLink products What special power supply decoupling is required for HOTLink products?	Not yet rated	06/10/11
Relationships between TXCLK, RXCLK and REFCLK for the CY7C924ADX in asynchronous mode What is the relationships between TXCLK, RXCLK and REFCLK for the CY7C924ADX in asynchronous mode?	Not yet rated	06/10/11
Are the receiver discard policies affected when the FIFO's are bypassed in the CY7C924ADX? Are the receiver discard policies affected when the FIFO's are bypassed in the CY7C924ADX?	Not yet rated	06/10/11
Part Naming conventions for HOTLink 2 parts How are the HOTLink 2 parts named ?	Not yet rated	02/26/11
What is the FIT (Failure in Time) rate, or MTBF (Mean Time Before Failures) of the CY7C9689A? What is the FIT (Failure in Time) rate, or MTBF (Mean Time Before Failures) of the CY7C9689A?	Not yet rated	02/03/11
HOTLink DX PECL Output to LVTTL Input - How do I connect the differential PECL outputs of the CY7C924ADX or CY7C9689A to a single-ended LVTTL input? - Is it possible to use a LVTTL optical module? - How do I make a PECL to LVTTL translation?	Not yet rated	02/03/11

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