Interfacing a PSoC® 3/4/5LP SPI Master Component to SPI Slave Chips – KBA88268 Question: When using PSoC® 3/4/5LP as an SPI master to interface with SPI slaves (such as SPI EEPROMs, SPI-based ADCs, etc.), the data read from / written to the slaves is wrong when CPU speed is decreased (or SPI speed is increased). However, the data is correct for faster CPU speeds (or for slower SPI clock frequencies). What is a possible cause for this issue and how do you fix it?
Calibrating Internal References in PSoC® 1 - KBA88270 Question: When calibrating the internal reference (such as a band gap reference) in PSoC® 1, you may need to bring the reference out to a GPIO pin. However, the analog output buffer would add some offset voltage to any internal analog signal before it is brought out to a GPIO pin. Is there any way to avoid this offset addition, so as to view the exact internally generated reference?