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Title Customer Rating Updated
Reference Schematic Design Recommendation for QDR-DDR II/II+/Xtreme SRAMs - KBA84386
Question: How to get a recommended reference schematic design for QDR-DDR II/II+/Xtreme products?
Not yet rated 		11/20/12
Input Jitter Requirements for 65 nm QDRII/II+/DDRII/II+ Device Family - KBA84380
Question:What are the input jitter requirements for 65 nm QDRII/II+/DDRII/II+ device family?
Not yet rated 		11/20/12
How to Resolve QDR-DDR II/II+/Xtreme Verilog Model Simulation Error Using Synopsys VCS - KBA84385
Question:Why Synopsys VCS gives incorrect simulation result with QDR-DDR II/II+/Xtreme verilog models?
Not yet rated 		11/20/12
Unused BWSb Pin Termination for ODT Enabled QDR-II+/DDR-II+ SRAM Devices - KBA82774
Question: Explain termination options for unused BWS pins.
Not yet rated 		11/07/12
Termination of Input pins in Sync SRAMs - KBA82779
Question: Do all input pins need pull up resistors for termination ?
Not yet rated 		11/07/12
I/O Switching Power for Sync SRAM - KBA82208
Question: Is the IDD (VDD operating supply current) current specified in the Sync SRAM datasheets sum of both the core current and I/O current?
(4/5) by 1 user 		10/18/12
Removal of External Pull-up Resistor (R) to Vt on D bus, BWSb, and K/Kb Clocks for QDR II+ and DDRII+ ODT Parts - KBA82936
Question: Can the external pull-up resistor (R) to Vt on D bus, BWSb, and K/Kb clocks be removed for QDRII+ and DDRII+ ODT enabled parts?
Not yet rated 		10/10/12
Back to Back Write in Synchronous SRAMs - KBA82781
Question: Can /WE be kept LOW during back-to-back write or does it has to be toggle on every write on this back-to-back transaction in Synchronous SRAMs?
Not yet rated 		10/03/12
Footprint / Landpattern of an SRAM?
Where can i get recommended footprint / Landpattern for standard packages?
Not yet rated 		09/12/12
Types of Burst Modes in Single Data Rate Synchronous SRAMs - KBA80733
Question: What are the types and functions of burst modes in Standard Sync/NoBL SRAMs (single data rate synchronous SRAMs)?
Not yet rated 		06/26/12
Burst Operation for QDR and DDR Synchronous SRAM Families - KBA80731
Question: How does the burst feature work in QDR and DDR SRAMs, and what are its advantages?
Not yet rated 		06/26/12
Advantages of Burst Modes in Single Data Rate Synchronous SRAMs- KBA80732
Question: What are the advantages of burst modes in Standard Sync/NoBL SRAMs (Single data rate synchronous SRAMs)?
Not yet rated 		06/26/12
Maximum Junction Temperature and Power Consumption Calculator
How can I find the power consumption, maximum junction temperature and absolute maximum temperature of an SRAM part ?
(4/5) by 1 user 		05/07/12
Address pin numbering in QDR II SRAMs
Why are the address lines not numbered in the pin out section of the QDR II datasheet?
Not yet rated 		04/18/12
Why do your address pins not match Samsungs or other vendors?
Parts by other vendors are obsolete. In the Cypress equivalent part the address and data lines are different. Can i use Cypress part without changes in firmware?
Not yet rated 		04/16/12
Considerations when migrating from Samsung to Cypress QDRII/DDRII SRAMs
What are the considerations that need to be made when migrating from Samsung to Cypress QDRII/DDRII SRAMs
Not yet rated 		03/29/12
Vss and Vcc clarification
Which pin is ground: Vcc or Vss?
Not yet rated 		03/13/12
Floating data input on CMOS SRAM
I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?
Not yet rated 		03/13/12
Do Address pins have internal Pull-up or Pull-down circuits?
Do you have internal pullups or pulldowns on your address pins so that they may be left floating?
Not yet rated 		03/13/12
Do you have Land Patterns or layouts
Do you have a recommended land pattern for my Cypress device?
Not yet rated 		03/13/12
Does
What does the 'T' at the end of some part numbers mean?
Not yet rated 		03/13/12
DRAM Availability
Does Cypress make DRAM?
Not yet rated 		03/13/12
How to Submit Parts for FA
How can I send a device in for failure analysis?
Not yet rated 		03/13/12
DLL Considerations in QDRII/DDRII SRAMs
How do QDRII/DDRII SRAMs behave in DLL disabled mode
Not yet rated 		03/07/12
Address and I/O Pin Order Flexibility for the Standard Synchronous and NoBL™ SRAMs
Address pin and I/O pin order
Not yet rated 		03/07/12
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