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Title	Customer Rating	Updated
Footprint / Landpattern of an SRAM? Where can i get recommended footprint / Landpattern for standard packages?	Not yet rated	09/12/12
Why do your address pins not match Samsungs or other vendors? Parts by other vendors are obsolete. In the Cypress equivalent part the address and data lines are different. Can i use Cypress part without changes in firmware?	Not yet rated	04/16/12
Vss and Vcc clarification Which pin is ground: Vcc or Vss?	Not yet rated	03/13/12
Floating data input on CMOS SRAM I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?	Not yet rated	03/13/12
Do Address pins have internal Pull-up or Pull-down circuits? Do you have internal pullups or pulldowns on your address pins so that they may be left floating?	Not yet rated	03/13/12
Do you have Land Patterns or layouts Do you have a recommended land pattern for my Cypress device?	Not yet rated	03/13/12
Does What does the 'T' at the end of some part numbers mean?	Not yet rated	03/13/12
How to Submit Parts for FA How can I send a device in for failure analysis?	Not yet rated	03/13/12
Moisture Sensitivity Level (MSL) of Cypress Parts How do I find Moisture Sensitivity Level (MSL) of Cypress parts?	Not yet rated	09/08/11
Semaphore Value in Asynchronous Dual-Ports - What are the uses of Semaphore latches? - How are semaphore values read on the I/O bus?	Not yet rated	06/27/11
cross-section drawings and thickness ? Where do I Request a cross-section drawing with layers labeled and nominal thickness that can be identified?	Not yet rated	06/26/11
SRAM Environmental Testing Where is the environmental and mechanical testing data available.	Not yet rated	06/20/11
FIFOs vs Dual-ports When is a FIFO used instead of a dual port? How do I select between a FIFO and dual-port for my application?	(3/5) by 1 user	06/11/11
Aggregate bandwidth and throughput of synchronous dual-ports - How do you calculate bandwidth with dual-ports? - What is the throughput of a particular dual-port?	Not yet rated	06/11/11
Using multiple devices to create a wider data path for synchronous dual port SRAM's How can multiple dual-port devices be combined to create a wider data path? Can I width cascade multiple dual-ports? How would I set up the dual-port for width expansion?	Not yet rated	06/11/11
Depth and width expansion affect on board-level timing How does memory depth and width expansion affect board-level timing?	(5/5) by 1 user	06/11/11
CY7C08xxV Read Cycle Latency - Why is there no FT/PL pin in some of the synchronous dual-ports? - What is the latency associated with read operations?	Not yet rated	06/11/11
Battery backed solutions for CY7C08xxV dual-ports Why is the standby current rating (Isb) on these 2Mb (CY7C0851V) and 4Mb (CY7C0852V) dual-ports so high compared to the 1Mb devices? I would expect the difference in Isb to be fairly linear, but it is, in fact, several orders of magnitude greater. (10 mA vs. 10-50uA). The complication comes in looking for a battery backup switcher. I've found none of these power monitors can handle >150uA of standby current. Does Cypress have an battery backed solution available for these high-density dual-ports?	Not yet rated	06/11/11
Simultaneous access in synchronous dual-ports - Can I write to the dual-port at the same time from both ports? - What happens when I read and write to the same location at the same time? - What happens if I read from the same location at the same time? - If both ports are running off the same clock how may clock cycles after I write can I initiate a read from the same address?	(4/5) by 1 user	06/11/11
Read-Back of Internal Address Counters for synchronous dual port SRAM's - How can one see the current state of the internal counter? - Is there a way to check the state the burst counter? - Is address readback different for the CY7C08x1V / CY7C08x2V devices?	Not yet rated	06/11/11
Unused OE# and CE1 Pins If I am not going to use these pins, what should I do with them?	Not yet rated	06/11/11
VSS vs. VSSQ for synchronous dual port SRAM's What is the difference between VSSQ versus VSS in the datasheet?	Not yet rated	06/11/11
Burst Counter Operation and chip disabled for synchronous dual port SRAM's If I do a read or write of a number of words and I use the internal counter (ie load the counter start address on the first word and then count after that), but I only give a CE (chip enable) every other clock; will I read data from consecutive address locations every other clock? An example: For a burst read -- first clock load counter, second clock do nothing, third clock give chip enable and read first data, fourth clock do nothing, fifth clock give chip enable and read second data (next one in memory after first), sixth clock do nothing, seventh clock give chip enable and read third data, etc. Note that output enable and counter enable will always be active. Could you confirm this for me?	(5/5) by 1 user	06/11/11
Read and Write with Single Internal Counter for Synchronous Dual port SRAM's What happens if we write on one clock cycle with ADS#, CE# and CNTEN# all low (i.e. load the address counter) and then, on the next cycle we read without ADS# but with CNTEN# (i.e. increment the counter). Will the address we read from be one higher than the one we loaded in the first cycle?	Not yet rated	06/11/11
Timing relationship of OE# to the dual-port What is the timing relationship between OE# and CE# in synchronous Dual Ports? - How is the output enable signal connected to the clocks?	Not yet rated	06/11/11

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