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Title Customer Rating Updated
Footprint / Landpattern of an SRAM?
Where can i get recommended footprint / Landpattern for standard packages?
Not yet rated 		09/12/12
Why do your address pins not match Samsungs or other vendors?
Parts by other vendors are obsolete. In the Cypress equivalent part the address and data lines are different. Can i use Cypress part without changes in firmware?
Not yet rated 		04/16/12
Vss and Vcc clarification
Which pin is ground: Vcc or Vss?
Not yet rated 		03/13/12
Floating data input on CMOS SRAM
I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?
Not yet rated 		03/13/12
Do Address pins have internal Pull-up or Pull-down circuits?
Do you have internal pullups or pulldowns on your address pins so that they may be left floating?
Not yet rated 		03/13/12
Do you have Land Patterns or layouts
Do you have a recommended land pattern for my Cypress device?
Not yet rated 		03/13/12
Does
What does the 'T' at the end of some part numbers mean?
Not yet rated 		03/13/12
How to Submit Parts for FA
How can I send a device in for failure analysis?
Not yet rated 		03/13/12
Moisture Sensitivity Level (MSL) of Cypress Parts
How do I find Moisture Sensitivity Level (MSL) of Cypress parts?
Not yet rated 		09/08/11
Synchronous FIFO Flag Update Cycle
- What is the Flag Update Cycle? - Must the FIFO be read to update the empty flag? - Must the FIFO be written to for the full flag to be updated?
Not yet rated 		06/27/11
Usage of the Vcc/SMODE# pin

Not yet rated 		06/27/11
cross-section drawings and thickness ?
Where do I Request a cross-section drawing with layers labeled and nominal thickness that can be identified?
Not yet rated 		06/26/11
Master Reset cycle
- How to reset the FIFO? - How to operate /MR? - What is a proper reset?
Not yet rated 		06/23/11
SRAM Environmental Testing
Where is the environmental and mechanical testing data available.
Not yet rated 		06/20/11
Read / Write control signals on unidirectional FIFOs
Why is there a read/write control signal (R/W#) on each port for a unidirectional FIFO?
Not yet rated 		06/18/11
Writing at the Full Boundary
- What happens if FIFO is continuously write into when Full Flag is asserted? - My system is set up to continuously write until the FIFO is full. Once it is full, I begin to read out the data. However, it seems like I lose some of the data being written into the FIFO when I do so. RCLK and WCLK are the same. What is wrong?
Not yet rated 		06/17/11
Usage of the Output Enable (OE) Signal in Synchronous FIFOs
1. If OE is high, what happens to the data bus? 2. If there is a valid read operation, but OE is high, will the next read operation be the same word or the following word in the FIFO? 3. If OE is high during reset, will the data bus remain in a high-Z state? 4. Is it okay to connect the OE pin to ground?
Not yet rated 		06/17/11
Synchronous FIFO architecture
What is the architecture of the Synchronous FIFOs? Is the memory managed by pointers or shifting registers? If the fullness of the FIFO is managed well, is it possible to endlessly read and write?
Not yet rated 		06/17/11
Usage of different speed grades in synchronous FIFOs
- Can I replace a -35 device with with a -25 device? - If the two ports of my FIFO are running at different rates, how do I pick a speed grade for my system?
Not yet rated 		06/17/11
Driving REN1 and REN2 together for some families of synchronous FIFO's
- Can I drive /REN1 and /REN2 with the same signal? - Can I tie Read Enable 1 and Read Enable 2 together?
Not yet rated 		06/17/11
Retransmit feature of synchronous FIFO's
- What happens to the data lines when RT is pulsed and during the tRTR time? - Can a selected block of data be retransmitted? - What considerations are there for using the retransmit operation?
Not yet rated 		06/17/11
Delay buffers using synchronous FIFOs
How can I make a delay buffer that always has x number of words in the buffer?
Not yet rated 		06/17/11
Synchronous FIFO Clocks
- Are there any requirements for clock duty cycles? - Do the clocks have to have 50 percent duty cycles? - What are the requirements for the clock driving sync FIFOs?
Not yet rated 		06/17/11
Output State for the FIFOs
- Can I make the data outputs (Q0 - Q8) to be normally high? - What is the status of the data outputs after reset? - What happens to the data outputs when /OE is asserted?
Not yet rated 		06/17/11
Driving 3.3V I/Os on a 5V device
- Can I drive 3.3V I/Os into a 5V part? - What are the minimum input levels for 5V devices? - Will my 3.3V processor be strong enough to connect to a 5V device? - Will a -1V undershoot on the inputs cause problems?
Not yet rated 		06/17/11
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