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Title	Customer Rating	Updated
Generation of FIFO Empty and Full Flags - KBA85082 Question: How are FIFO empty and full flags generated?	Not yet rated	04/04/13
Footprint / Landpattern of an SRAM? Where can i get recommended footprint / Landpattern for standard packages?	Not yet rated	09/12/12
Why do your address pins not match Samsungs or other vendors? Parts by other vendors are obsolete. In the Cypress equivalent part the address and data lines are different. Can i use Cypress part without changes in firmware?	Not yet rated	04/16/12
Vss and Vcc clarification Which pin is ground: Vcc or Vss?	Not yet rated	03/13/12
Floating data input on CMOS SRAM I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?	Not yet rated	03/13/12
Do Address pins have internal Pull-up or Pull-down circuits? Do you have internal pullups or pulldowns on your address pins so that they may be left floating?	Not yet rated	03/13/12
Do you have Land Patterns or layouts Do you have a recommended land pattern for my Cypress device?	Not yet rated	03/13/12
Does What does the 'T' at the end of some part numbers mean?	Not yet rated	03/13/12
How to Submit Parts for FA How can I send a device in for failure analysis?	Not yet rated	03/13/12
Availability of FIFO parts CY7C460, CY7C462, CY7C464 & CY7C466 Question: Where can we look for information on the following FIFO parts CY7C460, CY7C462, CY7C464 & CY7C466?	(4/5) by 2 users	12/28/11
Aggregate bandwidth and throughput of synchronous FIFOs - How is the aggregate bandwidth of a synchronous FIFO calculated? - How is the aggregate throughput of a synchronous FIFO calculated?	Not yet rated	12/28/11
Programming the Almost Empty / Almost Full (PAE, PAF) Flags - How do I program the PAE and PAF flags? - What is the valid range for PAE and PAF flags? - How do I store the PAE and PAF values?	Not yet rated	12/28/11
Read Pointer operation in CY7C42x1 FIFOs - Is the address pointer incremented when REN1 & REN2 are asserted, RCLK is toggled, but OE is not asserted? - What happens if RCLK is toggled, but only REN1 is asserted (REN2 is not)?	Not yet rated	12/28/11
Tapped Serial Delay Lines Using FIFOs How can you implement a tapped serial delay line using a FIFO?	Not yet rated	12/28/11
Tying two (unidirectional) FIFO outputs together Can I safely tie two outputs together in case of depth cascading? or How should I set up my system to switch from one data bus to another when using two FIFOs? or Can I use the output enables (OE#) to switch from one bus to another if they are tied together?	Not yet rated	12/28/11
Moisture Sensitivity Level (MSL) of Cypress Parts How do I find Moisture Sensitivity Level (MSL) of Cypress parts?	Not yet rated	09/08/11
Load Capacitance of Tri-State Data bus of many SRAMs connected together What will be the load capacitance of a Tri-State Data bus when more than one SRAM busses are connected together?	Not yet rated	09/01/11
Synchronous FIFO Flag Update Cycle - What is the Flag Update Cycle? - Must the FIFO be read to update the empty flag? - Must the FIFO be written to for the full flag to be updated?	Not yet rated	06/27/11
Usage of the Vcc/SMODE# pin	Not yet rated	06/27/11
cross-section drawings and thickness ? Where do I Request a cross-section drawing with layers labeled and nominal thickness that can be identified?	Not yet rated	06/26/11
Master Reset cycle - How to reset the FIFO? - How to operate /MR? - What is a proper reset?	Not yet rated	06/23/11
SRAM Environmental Testing Where is the environmental and mechanical testing data available.	Not yet rated	06/20/11
Read / Write control signals on unidirectional FIFOs Why is there a read/write control signal (R/W#) on each port for a unidirectional FIFO?	Not yet rated	06/18/11
Writing at the Full Boundary - What happens if FIFO is continuously write into when Full Flag is asserted? - My system is set up to continuously write until the FIFO is full. Once it is full, I begin to read out the data. However, it seems like I lose some of the data being written into the FIFO when I do so. RCLK and WCLK are the same. What is wrong?	Not yet rated	06/17/11
Usage of the Output Enable (OE) Signal in Synchronous FIFOs 1. If OE is high, what happens to the data bus? 2. If there is a valid read operation, but OE is high, will the next read operation be the same word or the following word in the FIFO? 3. If OE is high during reset, will the data bus remain in a high-Z state? 4. Is it okay to connect the OE pin to ground?	Not yet rated	06/17/11

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