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Title Customer Rating Updated
Routing Clocks in QDR/DDR Sync SRAM – KBA89151
Question: Should the clocks in QDR/DDR Sync SRAMs be routed as single-ended or differential?

Not yet rated
04/04/14
Nature of Clock Phase Jitter in DDR/QDR™ Sync SRAM – KBA89153
Question: What type of jitter is specified by tKC Var (clock phase jitter) in DDR/QDR™ Sync SRAM?

Not yet rated
04/04/14
Dummy Read Cycle – KBA89262
Question:What is the significance of the dummy read cycle in SynC SRAMs?

Not yet rated
03/27/14
K/K# Clocks Routing for QDR®II/II+/DDRII/DDRII+ SRAMs – KBA89248
Question: Should you treat the K/K# clocks as single-ended or as differential signals in PCB routing?

Not yet rated
03/18/14
Initial Contents of an F-RAM™ Device Shipped From the Factory - KBA91030
Question: What are the contents of a Cypress® F-RAM™ device when it is shipped from the factory?

Not yet rated
03/17/14
Reference Schematic Design Recommendation for QDR®-DDR II/II+/Xtreme SRAMs – KBA84386
Question: Where can I get a recommended reference schematic design for QDR®-DDR II/II+/Xtreme products?

Not yet rated
03/05/14
Drive Current for FRAM /RST Pin - KBA88165
Question: What is the maximum drive current of the /RST (lmax) for the FRAM part FM31278?

Not yet rated
12/26/13
FRAM Contents when shipped from Cypress – KBA88164
Question: Are FRAM contents programmed when shipped from Cypress? How is this different from an EEPROM?

Not yet rated
12/17/13
Depth Expansion of CY7C42x1 / CY7C42x1V Synchronous FIFOs

Not yet rated
12/13/13
Understanding of Voh and Vol of QDR (QDR, QDR-II/II+ & QDR-II+ Xtreme) SRAMs - KBA82773
Question: Why do the Voh and Vol of QDR SRAMs (QDR, QDR-II/II+ & QDR-II+ Xtreme) have the same range in the DC specs section of the datasheet?

Not yet rated
11/25/13
CY7C419 / 421 / 425 / 429 / 433 Pin Configuration for SOJ package
What is the pin configuration of the molded SOJ package

Not yet rated
11/22/13
Knowledge Base – Cypress Semiconductor Cage Code – KBA89258
Question: What is Cypress Commercial and Government Entity Code or CAGE CODE?

Not yet rated
09/27/13
Separate Supplies for VTT and VREF – KBA88203
Question: Can VTT be tied to VREF while designing with QDR™-DDR II/II+/Xtreme devices?

Not yet rated
09/13/13
Significance of the Write Enable Latch (WEL) Bit in Serial SPI FRAM and the Write Enable (WEN) Bit in Serial SPI nvSRAM - KBA88148
Question: What is the significance of the Write Enable Latch (WEL) bit in the status register of serial SPI FRAM and the Write Enable (WEN) bit in the status register of serial SPI nvSRAM?

Not yet rated
09/13/13
The /W Pin and VDD - KBA88151
Question: Should the /W pin be tied to VDD if it is not used in SPI FRAM devices?

Not yet rated
09/12/13
nvSRAM Definition - KBA87014
Question: What is nvSRAM?

Not yet rated
08/22/13
Generating VREF and VTT in QDR®, DDR-II, DDR-II+, and Xtreme SRAMs - KBA85112
Question: How do I generate VREF and VTT in QDR®, DDR-II, DDR-II+, and Xtreme SRAM devices?

Not yet rated
07/17/13
Initial Contents of an nvSRAM Device - KBA83096
Question: What are the contents of an nvSRAM device when it is shipped? Can I assume that the data is fixed?

Not yet rated
06/26/13
Introduction to F-RAM - KBA87028
Question: What is F-RAM?

Not yet rated
06/10/13
ADV pin to a static level? Should I toggle it during normal operation?">Connecting the ADV Pin to a Static Level - KBA83097
Question: Can I connect the ADV pin to a static level? Should I toggle it during normal operation?

Not yet rated
05/31/13
Generation of FIFO Empty and Full Flags - KBA85082
Question: How are FIFO empty and full flags generated?

Not yet rated
04/04/13
nvSRAM operation at ambient temperature beyond value specified in datasheet - KBA82775
Question: Can an industrial temperature range nvSRAM part be used in applications where the ambient temperature occasionally exceeds 85 °C?

Not yet rated
02/25/13
Input Jitter Requirements for 65 nm QDRII/II+/DDRII/II+ Device Family - KBA84380
Question:What are the input jitter requirements for 65 nm QDRII/II+/DDRII/II+ device family?

Not yet rated
11/20/12
How to Resolve QDR-DDR II/II+/Xtreme Verilog Model Simulation Error Using Synopsys VCS - KBA84385
Question:Why Synopsys VCS gives incorrect simulation result with QDR-DDR II/II+/Xtreme verilog models?

Not yet rated
11/20/12
Unused BWSb Pin Termination for ODT Enabled QDR-II+/DDR-II+ SRAM Devices - KBA82774
Question: Explain termination options for unused BWS pins.

Not yet rated
11/07/12
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