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Results 1 - 14 of 14

Title	Customer Rating	Updated
SX2's response to SET_INTERFACE request How is SX2's response to SET_INTERFACE request different from its response to other EP0 requests ?	Not yet rated	04/30/12
Returning a NAK from the CY7C68001 EZ-USB SX2 to the USB Host The USB 2.0 specification says that when the USB host sends an IN token to a device, and if the device has no data to return to the host, it should respond with a NAK token. However, the CY7C68001 datasheet says there is no description and no register corresponding to generation of a NAK token. How does one return a NAK token using the SX2? Does the external master have to construct one?	Not yet rated	06/19/11
SX2 device displayed as an 'Unknown device' on device manager. While using the default SX2 descriptors as provided in section 12.0 of REV D version of the datasheet and the VID/PID reported in the device descriptor bound to the ezusb.sys driver (via the ezusbw2k.inf file). When the device is plugged in, it fails to enumerate and shows up as an "Unknown device" in the device manager. What could be the problem?	Not yet rated	06/19/11
Slave FIFO Mode Synchronous Burst Read/Write with the CY7C68013 (FX2) Does the FX2 device support synchronous burst read/write in slave FIFO mode? In the FX2 Technical Reference Manual, I am unable to find an I/O waveform of synchronous burst read/write with SLRD/SLWR asserted for the entire burst duration.	Not yet rated	06/17/11
Reset Signal High Duration for the CY7C68001 EZ-USB SX2 Does it matter how long the reset line is hold at high before going to reset?	Not yet rated	06/10/11
CY7C68001 EZ-USB SX2 INT# Pin Behavior for Multiple Interrupts. The EZ-USB SX2 is capable of buffering multiple interrupts and INT# should be asserted if there is one or more pending interrupts. Must multiple interrupts be captured by an edge-triggered or level-triggered interrupt pin on the external master? For example, when there are two pending interrupts, reading the interrupt status byte clears the first interrupt. However, there is still one more pending interrupt, so the INT# line should be asserted again. INT# ___/ \__ (1) (2) INT# ______ (1) (2) Which waveform is correct?	Not yet rated	06/10/11
Handling of USB bus reset by External master interfaced to SX2 How does the external master handle the case where SX2 receives a USB bus reset?	Not yet rated	06/10/11
Physical Interface and CPU Responsibilities for the SX2 What physical interface is presented to the external master or CPU from the EZ-USB SX2? What is the external master or CPU responsible for?	Not yet rated	06/09/11
SX2 Processor. Does the SX2 have a processor (8051 ) like the FX2? If so, how is it different from the FX2?	Not yet rated	06/09/11
CY3682 development kit contents Where can I find the CY3682 development kit contents?	Not yet rated	05/24/11
External Processor Connection to the Host with the CY7C68001 - EZ-USB SX2. How does a processor tell that the SX2 is connected to a host? When the processor gets connected, an ENUMOK interrupt gets sent using an EEPROM to load the descriptor. Is it safe to assume that if a BUSACTIVITY interrupt is seen that the processor is disconnected, and that if an ENUMOK interrupt is received it is connected? Or is there a better way to do this?	Not yet rated	04/03/11
Checking Enumerated Speed of the CY7C68001 EZ-USB SX2. How to know if the CY7C68001 EZ-USB SX2 has enumerated at full- or high-speed?	Not yet rated	04/03/11
SetFeature request in SX2 Who handles the SetFeature request in SX2? How does the SX2 support the test modes for electrical compliance testing as defined in section 7.1.20 of the USB 2.0 specification?	(3/5) by 1 user	03/29/11
Changing to FX2LP from SX2 How can the FX2LP be made to work like SX2?	(4/5) by 1 user	03/20/11

Results 1 - 14 of 14