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Title	Customer Rating	Updated
Avoiding overflow of RX FIFO in the CY7C924ADX and CY7C9689A. How to avoid RX FIFO overflow in the CY7C924ADX and CY7C9689A?	Not yet rated	12/07/11
Characteristics and considerations for HOTLink jitter What are the characteristics and considerations for HOTLink jitter?	Not yet rated	12/07/11
Data stream is always valid when RVS is LOW Is it guaranteed that the data stream is always valid when RVS is LOW?	Not yet rated	12/07/11
Moisture Sensitivity Level (MSL) of Cypress Parts How do I find Moisture Sensitivity Level (MSL) of Cypress parts?	Not yet rated	09/08/11
Interfacing the SO pin to CY7B933 If the SO pin is pulled up (the SI input now becomes the INB- input), and at a later time this pull up is removed (after device interface configuration) does the SO become an output of the SI signal?	Not yet rated	07/01/11
Are the FIFO's accessible (for either reads or writes) when the part enters BIST mode (CY7C924ADX or CY7C9689A) 1)Can I read characters from the RXFIFO during BIST mode (CY7C924ADX or CY7C9689A)? 2)Can I write characters to the TXFIFO during BIST mode (CY7C924ADX or CY7C9689A)?	Not yet rated	07/01/11
MTBF or FIT of the CY7B923/CY7B933 What is the MTBF or FIT of the CY7B923/Cy7B933?	Not yet rated	07/01/11
Is there a drop in replacement for the Cy7B923/933 LMB military package 1)Is there a drop in replacement for the Cy7B923/933 LMB military package? 2)Can I replace the Cy7B923/933-LMB with a -JC or -JI?	Not yet rated	07/01/11
Configure the HOTLink 1 for 3.3V I/O? Is there a way to configure the HOTLink 1 for 3.3V I/O?	Not yet rated	07/01/11
SMPTE standards supported by HOTLink family 1)How can I use the HOTLink1 parts in a SMPTE-259M application? 2)Does Cypress have a part that supports the SMPTE 310M video standard?	(4/5) by 2 users	07/01/11
Should I use HOTLink CY7C924ADX or CY7C9689A Should I use HOTLink CY7C924ADX or CY7C9689A?	Not yet rated	07/01/11
Configuration of the Status In (SI) and Status Out (SO) Pins 1) If I want to use the SO pin as a true output of SI, but the signal it is connected to is pulled up to Vcc during startup, will this affect the configuration of SO? 2) Can I change the state of SO is used during operation? 3) How is the function of the INB(INB+) input and the SI(INB-) input defined?	Not yet rated	07/01/11
Can the FIFO be bypassed in CY7C924ADX when using the byte-packer Can I bypass the FIFO in CY7C924ADX when I want to use 10-bit encoded mode?	Not yet rated	07/01/11
Unused serial inputs and outputs on HOTLink CY7B923/CY7B933 What should be done with unused serial inputs and outputs on HOTLink CY7B923/CY7B933?	Not yet rated	06/28/11
CY9266 Evaluation Board documentation 1)How do I test the CY9266 evaluation board? 2)What types of evaluation boards are available for testing the CY7B923/CY7B933? 3)How do I setup BIST on the CY9266 evaluation board?	Not yet rated	06/27/11
Meaning in datasheet, when it says that you can write to the FIFO from DC to 50 MHz What does the datasheet mean when it says that you can write to the FIFO from DC to 50 MHz?	Not yet rated	06/24/11
Reducing Power Dissipation: Unused serial outputs on CY7C9689 What do I do with the unused serial outputs OUTA±/OUTB± on the CY7C9689 device? Is there a setting that is particularly beneficial?	Not yet rated	06/24/11
Transformers recommendation for HOTLink CY7B9234 and CY7B9334 What transformers does Cypress recommend for HOTLink CY7B9234 and CY7B9334?	Not yet rated	06/24/11
Latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver. What is the latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver?	Not yet rated	06/24/11
Rad hardness, Soft Error Rate (SER), Single Event Upset (SEU) rates for the CY7B923 and CY7B933. What information do you have about rad hardness, Soft Error Rate (SER), Single Event Upset (SEU) rates for the CY7B923 and CY7B933?	Not yet rated	06/24/11
CKR outputs are unusable when the serial inputs to the CY7B933 are left floating and a REFCLK of 40MHz is supplied. When the serial inputs to the CY7B933 are left floating and REFCLK of 40MHz is supplied,Why are CKR outputs are unusable?	Not yet rated	06/24/11
SPDSEL and RANGESEL for 100MBaud (CY7C9689A, CY7C924ADX) 1) What would be the setting on the SPDSEL and RANGESEL, if the chip has to be operated at 100 MBaud? The speed may vary above or below 100 Mbaud and Refclk would be 20 MHz? 2) -Do you recommend a spread sprectrum clock?	Not yet rated	06/22/11
HOTLink II Three Level Control Inputs Can the 3-Level select static control inputs be controlled by an FPGA/CPLD output? (For CYP(V)15G0401DXB, CYP(V)15G0402DXB, CYP(V)15G0201DXB, and CYP(V)15G0101DXB).	Not yet rated	06/13/11
Switching between Serial Differential Inputs - How long does it take for HOTLInk II receiver to switch between the serial differential inputs from IN1(+/-) to IN2(+/-) - How long does it take for HOTLInk II receiver to switch between the serial differential inputs from IN1(+/-) to IN2(+/-) - IN1(+/-) is coming from an external link. OUT2(+/-) loop back's to IN2(+/-). Two channels have the same freq. Before the external link is established, we select IN2. We have plenty of time for the receiver to lock in IN2. When the external link on IN1 becomes OK, we switch the receiver to IN1. How long does it take for the clock recovery to lock in? Does it still take 376K UI?	Not yet rated	06/13/11
Considerations in Interfacing HOTLink II to Fiber Optic Module What are the considerations in Interfacing HOTLink II to Fiber Optic Module? How can I interface a SFP fiber optic module with HOTLink II?	Not yet rated	06/13/11

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