The comparator is the most fundamental building block of a mixed-signal design. It is essentially a differential amplifier with an extremely high open loop gain. In order to improve the stability of the output with noisy inputs, hysteresis is used in the design, by creating two thresholds - one threshold for the output to switch from low to high and another for the output to switch from high to low.

Hysteresis comparator in PSoC1 can be implemented using either of the following types of analog blocks:

1.    Continuous time (CT) analog block

2.    Switched capacitor (SC) analog block

The CT block in PSoC1 includes an opamp and a resistor array. This makes the analog block useful for functions such as programmable gain amplifier (PGA) and comparators. The SC block of PSoC1 includes an opamp with a switched capacitor network around it. This architecture is useful in the design of integrator, differentiator, filter, amplifier, DAC and comparator.

Hysteresis Comparator using SC Block

The COMP user module in PSoC Designer can be used to design hysteresis comparators using the CT block. It is also possible to make an SC block comparator with the hysteresis. The SC block comparator s threshold level is determined by the ratio of two internal capacitors. This produces a comparator with the hysteresis that:

• Has no external components
• Allows the hysteresis thresholds to be easily changed in firmware

Figure below shows an SC block configured as a programmable threshold comparator.

AN2108 PSoC1 Impementing Hysteresis Comparators describes a detailed example to show how SC blocks can be used for such a design in PSoC1. In addition, two other design examples are also shown, along with commented firmware projects:

Design 1 shows a hysteresis comparator implementation using a CT block and external resistors. This architecture allows precise setting of the hysteresis.

Design 2 shows a unique technique to implement a comparator with independently controllable hysteresis thresholds.

Please access the application note webpage to download the document and zip file containing the example projects.  

Every programmable semiconductor device, including PSoC has limited resources. Cypress PSoC devices feature dynamic reconfiguration that enables designers to reuse analog and digital resources and achieve greater levels of functionality.

Interrupts and Dynamic Reconfiguration

Dynamic reconfiguration allows digital and analog blocks to be shared between different user modules, performing different functions at different times. This requires designers to handle interrupts differently from normal PSoC usage and choose the ISR to execute, based on which user module is loaded at any given time. For example, a digital block may share functionality between a Timer and SPI user module. Each of these UMs have a unique interrupt service routine, however, they share the same interrupt vector.

Therefore, the interrupt vector must be routed to the ISR for the user module that is loaded when the interrupt occurs. It is best to place user modules in such a way that the number of shared interrupt vectors is minimized.

The code excerpt below is taken from the interrupt vector table located in boot.asm file.

org   2Ch    ;PSoC Block DCB03 Interrupt Vector

ljmp  Dispatch_INTERRUPT_11

reti

Normally this interrupt vector would have jumped to a routine with a name specific to the user module. The vector now jumps to a routine called Dispatch_INTERRUPT_11 instead of the user module s ISR. This interrupt handler consecutively checks each configuration that shares the block to determine the active one. When it finds the active configuration, it jumps to the appropriate ISR for the loaded user module. If many configurations share the same block, this function may take longer to execute. This also causes different interrupts to have different latencies.

For more information about setting up dynamic reconfiguration in PSoC along with an example project, please refer AN2104 Dynamic Reconfiguration using PSoC Designer.

The Cypress PSoC 1 product family offers several choices for implementing I²C in a design. These choices come in the form of user modules (UMs) that are found in the PSoC Designer IDE. The I²C communication itself is handled by a dedicated I²C hardware (HW) block which removes much of the I²C processing burden from the CPU, freeing the CPU to do more important real-time tasks.

Figure 1: I2C Hardware Block

The HW block is a serial to parallel processor designed to interface the PSoC 1 to an I²C bus. The HW block takes the burden off the CPU by providing support for HW detection of I²C status and generation of I²C signals.

EzI2Cs

The first user module to consider is the EzI2Cs UM. The EzI2Cs UM operates exclusively as a slave; there is no master version of EzI2C. The EzI2Cs UM is a firmware layer on top of the I²C hardware block. It requires minimal user knowledge of how the I²C bus works by allowing you to setup a data structure in user code, and exposing that structure to the I²C master. All I²C transactions happen in the background through interrupts. You need not worry about any of the I²C functionality once the user module is started in the main code.

I2CHW

This user module is a firmware layer on top of the I²C HW bloc and can be used as a slave, master, or multi-master slave. Unlike EzI2Cs, this user module requires more designer interaction. Status bits must be checked to see if an I²C transaction occurred. The main firmware also needs to check for error conditions on a transaction. Finally, user code must clear the status bits that are set.

For a detailed overview of the I2C block in PSoC1 and example usage of the user modules described above, please refer application note AN50987 - Getting Started with I2C in PSoC® 1.

The importance of system power consumption management cannot be overstated. The use of PSoC s sleep mode is a simple and efficient way to reduce overall current draw without limiting the functionality. Significant power savings can be realized if attention is given to the proper entry, use, and exit of sleep mode. When implemented in conjunction with other power-saving features and techniques, sleep mode can be extremely effective in reducing  the  overall power consumption in a PSoC-based design. Below are two examples of techniques to reduce the power consumption in sleep mode by disabling PSoC features that may remain active when the SLEEP bit is set.

Disable Analog Block References

PSoC Analog Blocks have individual power-down settings that are controlled by the firmware. The Analog Block References can be disabled  by a  write to the PWR bits [2:0] of the  ARF_CR register, similar to the code below:

ARF_CR &= 0xf8; //Turn off analog reference

Disable CT/SC Blocks

The continuous time (CT) blocks are powered down individually with a write to each ACBxxCRy or ACExxCRy register corresponding to the block s column. The switch capacitor (SC) blocks are similarly controlled by the ASCxxCRy or ASDxxCRy registers. The example below shows how to disable the CT and SC blocks for column zero.

ACB00CR2 &= 0xfc; // Disable CT Block

ASC10CR3 &= 0xfc; // Disable typeC SC block

ASD20CR3 &= 0xfc; // Disable typeD SC block

The CT blocks can remain in operation because they do not require a clock source. However, the SC blocks do not operate because there is no clock source for the switches.

Application Note AN47310 PSoC1 Power Savings Using Sleep Mode provides an overview of PSoC1 sleep mode basics and information on power-saving methods, and other sleep related considerations.