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Title
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Customer Rating
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Updated
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Gate and Transistors of CY2305 - KBA86887
Question: How many transistors and gates does the CY2305SXC-1HT part have?
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Not yet rated
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04/09/13 |
Clock Tree Generation Example
How can a single oscillator output of 50 MHz distributed to 30 boards with a differential output? In addition, on each board, this input needs to be distributed to 32 devices with CMOS/TTL inputs.
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Not yet rated
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09/27/12 |
Input Duty Cycle for CY2305 / CY2305C / CY2309 / CY2309C
What is the specification for the duty cycle of the input clock for CY2305 / CY2305C / CY2309 / CY2309C?
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Not yet rated
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08/03/12 |
Zero Ohm Resistor for pull up/down in CY7B991 Select Lines
Are there any functional issues with using a zero ohm resistor to set the level to low for each of the select inputs 4F0, 4F1, 3F0, 3F1, 2F0, and 2F1?
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Not yet rated
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07/25/12 |
Spread Spectrum Clock (SSC) Input to Cypress Clock Device
Can I give Spread Spectrum Clock (SSC) input to any Cypress Clock device?
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Not yet rated
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03/21/12 |
Theta JA and Theta JC of the CY2CC810 in the SSOP package
What are Theta JA and Theta JC of the CY2CC810 in the SSOP package?
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Not yet rated
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03/06/12 |
Reference frequency jitter requirement for the CY2308
What is the reference frequency jitter requirement for the CY2308?
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Not yet rated
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03/06/12 |
Clock behavior of CY26049 when reference fails
What happens when the reference of CY26049 fails?
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Not yet rated
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03/06/12 |
Input Rise Fall Times of CY2309
Are there any rise or fall time restrictions on the input of the CY2309? Are there any Schmitt Triggers?
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Not yet rated
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03/06/12 |
Over Voltage Tolerant Inputs of CY2CC910 Elaborated
What is the meaning of "Over voltage tolerant input" as mentioned in CY2CC910 Datasheet?
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Not yet rated
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12/29/11 |
PCI Express Clock Buffer Gen 1 or Gen 2
Can the CY28400 or CY28401 devices be used in PCI Express Gen 2 clock buffer applications?
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Not yet rated
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12/29/11 |
Undriven Inputs of CY7B991V
What is the best way to tie the unused inputs to avoid undriven inputs in the design?
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Not yet rated
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12/29/11 |
Maximum Operation Frequency For CY7B994V RoboClockII
The data sheet shows the maximum of the CY7B994V FS HIGH range as 200 MHz but the f'OUT specification has a 185 MHz maximum. Is there a contradiction here?
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Not yet rated
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12/29/11 |
Use An External Divider In The Feedback Loop For RoboClockII
Can an external divider be used in a feedback loop?
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Not yet rated
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12/29/11 |
Reason for Tracking Skew not Specified in CY7B994V
Can I get the tracking skew of CY7B994V?
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Not yet rated
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12/29/11 |
RoboClockII Drive Differential Loads
Can RoboClockII drive differential loads?
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Not yet rated
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12/29/11 |
Switch Between the Secondary Input and Primary Reference Input
The data sheet states that RoboClockII has "selectable reference input ... which allows smooth change over to a secondary clock source." What does this mean? Will the part automatically switch to the second reference input if the primary reference input goes dead?
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Not yet rated
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12/29/11 |
Three-Level Input Model of CY7B993/4V
What are the required voltage levels of a three level input? How do you model a three-level input?
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Not yet rated
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12/29/11 |
Maximum Skew With RoboClockII
What is the maximum achievable skew with RoboClockII?
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Not yet rated
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12/29/11 |
Difference Between Feedback Bank and Other Four Banks of RoboClockII
What is the difference between the feedback (FB) bank and the four other banks?
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Not yet rated
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12/29/11 |
Difference Between tODCV And tPWH / tPWL of RoboClock
What is the difference between tODCV and tPWH /tPWL?
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Not yet rated
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12/29/11 |
Use RoboClockII To Multiply A Frequency
How can a frequency be multiplied using RoboClockII?
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Not yet rated
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12/29/11 |
Differential Reference And Feedback Input Capability
How should the differential reference and feedback input be connected?
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Not yet rated
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12/29/11 |
Theta Ja, Jc for CY7B993 / CY7B994 RoboClockII
What are the Theta Ja and Theta Jc values for CY7B993 / CY7B994 RoboClockII?
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Not yet rated
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12/29/11 |
Difference in Maximum VCO and Output Frequencies of CY7B9945V
Why the maximum output frequency is 200MHz when the VCO frequency can go upto 800MHz in CY7B9945?
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Not yet rated
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12/29/11 |
Driving 3-level Inputs of RoboClock With a Tri-state Buffer
Are there any considerations to be mindful of when driving the 3-level inputs with a tri-state buffer?
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Not yet rated
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12/29/11 |
Definition of Propagation Delay (tPD) for RoboClockII
What is the definition for Propagation Delay (tPD) for RoboClockII?
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Not yet rated
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12/29/11 |
Power-up Condition Cause A Device To Misbehave For 5V RoboClock
Are there any power-up conditions that cause the part to misbehave for 5V RoboClock?
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Not yet rated
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12/29/11 |
3.3V-Compatible RoboClocks
What all RoboClocks are 3.3V-compatible?
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Not yet rated
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12/29/11 |
REF Input Frequency Range for RoboClock
What is the REF input frequency range for RoboClock?
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Not yet rated
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12/29/11 |
Configuring CY7B994V for 33, 66, 100 and 133 MHz Outputs
Can CY7B994V output 33, 66, 100, 133 MHz simultaneously?
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Not yet rated
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12/29/11 |
Spread Aware Characteristics of Roboclock family
Do all RoboClock family parts have Spread Aware Characteristics?
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Not yet rated
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12/29/11 |
CY7B9973V Programmable Skew Support
Does the CY7B9973V device support programmable skew?
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Not yet rated
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12/29/11 |
Input jitter tolerance of CY7B993V and CY7B994V
What amount of jitter can the CY7B993V & CY7B994V REF inputs tolerate?
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Not yet rated
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12/29/11 |
Theta JC and JA Values for CY7B9930V
What are Theta JC and JA for CY7B9930V?
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Not yet rated
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12/29/11 |
Input Tolerance of CY7B9950
Is the input of CY7B9950 5V tolerant?
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Not yet rated
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12/29/11 |
External Divider Usage in Feedback Loop of RoboClockII
Is it possible to use an external divider in the feedback loop of the RoboclockII ?
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Not yet rated
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12/28/11 |
Internal Pull-Down Value for DISx pins of CY7B994V
What is the value of the internal pull-down for DIS1, DIS2, DIS3 and DIS4 inputs on the CY7B994V?
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Not yet rated
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12/28/11 |
Effect on Output with missing Reference Clock Cycles in CY7B993/994 Roboclocks
What will happen to the output clock when one cycle of the Reference Clock goes dead? Would it be the same with 100 cycles?
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Not yet rated
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12/28/11 |
Premis SSCG filter values below 1%
I need to set the FS781 filter values to give 0.3%, 0.5% and 0.7% spread bandwidth. They are running at 32MHz. What would the capacitor values be?
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Not yet rated
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12/28/11 |
Top Part Product Marking decipher key for SOIC 8 packages
Can you provide me with the Top Side product Marking especially date code description\decipher key for SOIC8 packages?
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Not yet rated
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12/28/11 |
Standard used to find MTBF/FIT
Which standard Cypress use to find MTBF/FIT?
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Not yet rated
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12/28/11 |
Effect of Crystal Capture Range Exceeded in Failsafe Clock
What happens when the reference frequency changes beyond the capture-range of the crystal oscillator?
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Not yet rated
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12/28/11 |
Cypress Clock Device as Level Translator
Can I give low voltage input clock to Cypress clock device operating with supply voltage higher than input clock signal voltage and get high voltage clock output?
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Not yet rated
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12/27/11 |
Phase Jitter and its measurement frequency range
What is phase jitter and over what frequency range it should be measured?
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Not yet rated
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12/27/11 |
PLL bandwidth and its impact on PLL output clock jitter
What is PLL bandwidth and how does it impact PLL output jitter?
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Not yet rated
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12/27/11 |
Interface LVPECL to LVDS
How do I convert to LVDS signals from LVPECL output lines.
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Not yet rated
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12/27/11 |
CY2DP818 LVPECL Driving A 2.5V CMOS Input
How can a 2.5V ASIC be protected when interfacing to the 3.3V CY2DP818?
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Not yet rated
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12/27/11 |
Pin skew with different loading on CY2CC810
If one pair is loaded at 5 pf, one pair of pins at 10 pf, and two pins left open, what effect will that have regarding pin to pin skew given your specification?
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Not yet rated
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12/27/11 |
Input tolerance of CY2CC910 at 1.8V and 2.5V Operation
When operating the CY2CC910 at 1.8, are the inputs 2.5v tolerant? The feature description implies that it does voltage conversion for 1.8/2.5/3.3v however, Vih max is 2.2v with vdd = 1.8v.
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Not yet rated
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12/27/11 |