Dec 12, 2011
PSoC Creator 2.0 is now on the web with some valuable new components:
While you're working with these new components, we are busy working on the next set of new components. Rather than make you wait until PSoC Creator 2.1 before you see more new components, we have another new feature in Creator 2.0 that allows us to provide you new components much more quickly. The new feature is the capability to provide a Component Pack. With a Component Pack we can deliver brand new components and deliver new versions of existing components. We'll do this without changing PSoC Creator and without requiring a full new installation. You can install a new component pack quickly and then you can choose when to start using these new components and new component versions all without impacting what version of Creator is building your current designs. We have several new components that are finishing up now that will go into the first Component Pack which will ship early next year. For those of you that like to dig a little deeper into how things work you may notice that with PSoC Creator 2.0 there is an additional library dependency called CyComponentLibraryUpdates that is included by default. This is the library that will contain the new and updated components that ship in a Component Pack. This library is currently empty. With each component pack this library will add content and then when PSoC Creator 2.1 ships they will all migrate into the base CyComponentLibrary and we'll start building this update library again. The PSoC Creator component catalog merges all the content from these libraries together into a single combined view, so you don't need to think about what library your content is coming from. This is just the mechanism that we've added with PSoC Creator to make these rapid releases of content possible.
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Mar 03, 2011
In an earlier post I provided a component that lets you use the datapath portion of the PSoC 3 / 5 UDB for its FIFO capability. In this post I’m providing components that let you take advantage of the registers within the datapath for storage. Each datapath has two 8-bit wide accumulators. The datapath has just one parallel input and one parallel output path, so only one value can be changed and only one value can be accessed at a time. The implementation that I’m providing configures the two bytes of storage as two registers in series. This provides two bytes of storage with a fixed delay from the data being clocked in to the data being clocked out. In some cases you might also want to store just a single byte and have access to that byte just like a conventional D Flip-Flop. A second component is provided for that case.
To create more storage these components can be configured in a series chain. An example usage for such a configuration is a filtering operation. For example the implementation of an average of 8 values filter will require the storage of the last 8 values. There are several ways that such a filter could be implemented. The brute force approach would be to store all 8 values in a chain and then add the last 8 values every clock cycle. There are two disadvantages to this approach. First this requires access to all 8 values and if the Delay2x8 component is used, only every other value is available. Secondly the computation of this sum will use 64 inputs to calculate the result and this will consume significant macrocell resources. An alternative implementation is to keep a running sum where the new value is added to the sum and the value from 8 clocks ago is subtracted from the sum. This fits well with the Delay2x8 component and uses far less macrocell resources. I’ve provided this example: DelayTest. You’ll also need the latest PSoC Sensei component library to have access to the Delay components. Below is how the Delay2x8 components are chained and connected to implement the average function.
 The average function has been written using Verilog and then synthesized into the macrocells by Creator. As you can see from the report file, this implementation is balanced between Datapath and Macrocell resources consuming about 20% of the digital resources in the device.
 The implementation of the average filter simply adds in the new value and subtracts out the old value and then shifts by 3 (divide by 8) to provide the result.
 In the example design provided I’ve used control and status registers to test the hardware operation without needing hardware test equipment. To accomplish this I’ve used an edge detector to enable the components for a single clock cycle under program control. That allows the hardware to step forward as the program that controls the test progresses.
 To test out this circuit you can bring the example up in the debugger. Then set breakpoints and also add a Watch on the i and avg variables. The picture below shows the results during the debug of an incrementing sequence.
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Feb 03, 2011
PSoC Creator is no longer Beta. It made the leap to a Production Release this week. It’s available for download now. If you already have a Beta version installed you can just upgrade with the installer from the Beta release. If you haven’t installed PSoC Creator yet, then you can find it at www.cypress.com/go/psoccreator and then click the Download button. With the Production release there are some new features and components. This post will discuss how to synchronize signals including how to use the new Sync component.
 PSoC 3 and 5 have considerable flexibility in the clocking mechanisms that are available. Throughout the digital logic array (UDB array) there are 9 low skew clocks available. One of these is always the bus clock (BUS_CLK). This is the clock that the system bus that runs throughout the device runs at. By default this is also the speed that the CPU is running at (PSoC 3 can support a divided CPU clock). There is another clock called the master clock (MASTER_CLK). This is the fastest clock in the system. It is possible to have BUS_CLK be divided down from MASTER_CLK, but I strongly encourage that you always have this divider set to 1 (that is the default). If you follow that recommendation BUS_CLK, MASTER_CLK and the CPU_CLK will all be the same frequency and the fastest clocks in the system. The other 8 clocks will be divided down versions of any of the clocks in the system. These clocks by default will be synchronized to MASTER_CLK. This is controlled by a check box in the clock customizer.
 You will generally want all your clocks synchronized to MASTER_CLK. That will allow easy communication between these clock domains and communication with the CPU or DMA. With all these clocks synchronous to MASTER_CLK a signal crossing between the domains will need to meet setup timing requirements within a MASTER_CLK period. When going from one clock domain to a slower clock domain the signal will need to be held long enough that it will be sampled by the slower clock domain, but there aren’t any asynchronous clock crossing issues.
Some signals in your system will likely come from sources that are asynchronous to the clock domain where they are used. The most common source for an asynchronous signal is an input pin. By default digital input pins are synchronized. This checkbox causes the input signal to be synchronized to BUS_CLK.
 Synchronization is done by a double synchronizer. Logically a double synchronizer is implemented as two back to back flip-flops.
 The theory behind this structure is that the signal may fail to meet the setup or hold time of the first flip-flop causing it to go to a metastable state. If that condition occurs it will settle to either 0 or 1 before the value gets clocked into the second flip-flop, so the value from the second flip-flop can be used with confidence that it will change only on the clock edge. A double synchronizer will introduce from 1 to 2 clock cycles of delay on the incoming signal.
The synchronizer for the input pin will be implemented directly at the pin if BUS_CLK is less than or equal to 33 MHz, and it will be implemented within the UDB array for higher speed clocks. When implemented within the array a special configuration of a Status register is used that can synchronize up to 4 signals to the same clock. PSoC Creator will automatically pack signals synchronized to the same clock. In either case the synchronization is done with BUS_CLK.
Synchronizing to BUS_CLK provides lower latency than synchronizing to a lower speed clock, but it places tighter timing constraints. Ideally signals should be synchronized to the same clock domain where they will be used. This can be accomplished by using the new Sync component which can be found in the component catalog in the System folder. For a pin the Sync can be used in place of the BUS_CLK synchronizer by turning off synchronization on the pin component and using the Sync component. The clock for the Sync component can be any clock in the system.
 The Sync component is always implemented with the special mode of the Status register. When reviewing the report file for resources utilized you’ll find separate entries for Status and Sync Cells, but they are using the same resources. To account for this the number listed as the Max Sync Cells is calculated as 4 times the Free Status registers.
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Jan 28, 2011
It turns out that even the PSoC Sensei makes mistakes. A customer was using the Transmit UART component and tried to build it for the PSoC 3 ES3 silicon. They found that it generated compiler errors. Shame on me for not testing the component with both ES2 and ES3. The fix was easy to implement and I've created a new version of the component with this fix. I’ll discuss in this post the process that is used to create a component version. PSoC Creator has versioning built into the tool. This allows me to release the fix for those customers that are in a place in their product development that they are able to integrate fixes. It also allows customers that are currently using the existing version to continue to use that version, just in case my fix breaks something else. The original version was version 1.0. That is designated by naming the component with “_v1_0” at the end. The new version is version 1.10. The 1 is referred to as the major version and the 10 is referred to as the minor version.
To update the existing instances the Component Update Tool should be launched from the menu Project->Update Components. This will provide the opportunity to select the version for each component instance that has multiple versions available. UARTTx_1 is the instance of interest in this example. Note that the Component Update Tool allows both upgrading and reverting to an older version if issues are found.
It also includes a link to the datasheet for the selected “Available Version”. The datasheet has a section that describes the changes made.
I’ve updated the library and made it available here: PSoC Sensei Library 01/27/2011. We’ve added a new capability to our
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Jan 19, 2011
In my post Creating Your Own Components I explained that there are 3 levels of component development:
At that point I had a set of 4 On-Demand Training classes (PSoC Creator 110 to 113) that explained the development of the first two component types. Now I'd like to point you to the latest On-Demand classes that are focused on datapath component development. Most of the digital components that Cypress provides in the standard library have been developed using datapaths and now the training is available to allow you to use the datapaths as well. There are a couple of reasons that you might want to consider using a datapath in your own components:
Developing datapath based components will require learning the way that a datapath is configured and that's why I've put together these training classes at www.cypress.com/go/training:
Now I'll get working on some new components.
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