Feb 03, 2011
PSoC Creator is no longer Beta. It made the leap to a Production Release this week. It’s available for download now. If you already have a Beta version installed you can just upgrade with the installer from the Beta release. If you haven’t installed PSoC Creator yet, then you can find it at www.cypress.com/go/psoccreator and then click the Download button.
With the Production release there are some new features and components. This post will discuss how to synchronize signals including how to use the new Sync component.
PSoC 3 and 5 have considerable flexibility in the clocking mechanisms that are available. Throughout the digital logic array (UDB array) there are 9 low skew clocks available. One of these is always the bus clock (BUS_CLK). This is the clock that the system bus that runs throughout the device runs at. By default this is also the speed that the CPU is running at (PSoC 3 can support a divided CPU clock). There is another clock called the master clock (MASTER_CLK). This is the fastest clock in the system. It is possible to have BUS_CLK be divided down from MASTER_CLK, but I strongly encourage that you always have this divider set to 1 (that is the default). If you follow that recommendation BUS_CLK, MASTER_CLK and the CPU_CLK will all be the same frequency and the fastest clocks in the system. The other 8 clocks will be divided down versions of any of the clocks in the system. These clocks by default will be synchronized to MASTER_CLK. This is controlled by a check box in the clock customizer.
You will generally want all your clocks synchronized to MASTER_CLK. That will allow easy communication between these clock domains and communication with the CPU or DMA. With all these clocks synchronous to MASTER_CLK a signal crossing between the domains will need to meet setup timing requirements within a MASTER_CLK period. When going from one clock domain to a slower clock domain the signal will need to be held long enough that it will be sampled by the slower clock domain, but there aren’t any asynchronous clock crossing issues.
Some signals in your system will likely come from sources that are asynchronous to the clock domain where they are used. The most common source for an asynchronous signal is an input pin. By default digital input pins are synchronized. This checkbox causes the input signal to be synchronized to BUS_CLK.
Synchronization is done by a double synchronizer. Logically a double synchronizer is implemented as two back to back flip-flops.
The theory behind this structure is that the signal may fail to meet the setup or hold time of the first flip-flop causing it to go to a metastable state. If that condition occurs it will settle to either 0 or 1 before the value gets clocked into the second flip-flop, so the value from the second flip-flop can be used with confidence that it will change only on the clock edge. A double synchronizer will introduce from 1 to 2 clock cycles of delay on the incoming signal.
The synchronizer for the input pin will be implemented directly at the pin if BUS_CLK is less than or equal to 33 MHz, and it will be implemented within the UDB array for higher speed clocks. When implemented within the array a special configuration of a Status register is used that can synchronize up to 4 signals to the same clock. PSoC Creator will automatically pack signals synchronized to the same clock. In either case the synchronization is done with BUS_CLK.
Synchronizing to BUS_CLK provides lower latency than synchronizing to a lower speed clock, but it places tighter timing constraints. Ideally signals should be synchronized to the same clock domain where they will be used. This can be accomplished by using the new Sync component which can be found in the component catalog in the System folder. For a pin the Sync can be used in place of the BUS_CLK synchronizer by turning off synchronization on the pin component and using the Sync component. The clock for the Sync component can be any clock in the system.
The Sync component is always implemented with the special mode of the Status register. When reviewing the report file for resources utilized you’ll find separate entries for Status and Sync Cells, but they are using the same resources. To account for this the number listed as the Max Sync Cells is calculated as 4 times the Free Status registers.
Jan 28, 2011
It turns out that even the PSoC Sensei makes mistakes. A customer was using the Transmit UART component and tried to build it for the PSoC 3 ES3 silicon. They found that it generated compiler errors. Shame on me for not testing the component with both ES2 and ES3. The fix was easy to implement and I've created a new version of the component with this fix. I’ll discuss in this post the process that is used to create a component version.PSoC Creator has versioning built into the tool. This allows me to release the fix for those customers that are in a place in their product development that they are able to integrate fixes. It also allows customers that are currently using the existing version to continue to use that version, just in case my fix breaks something else. The original version was version 1.0. That is designated by naming the component with “_v1_0” at the end. The new version is version 1.10. The 1 is referred to as the major version and the 10 is referred to as the minor version.
To update the existing instances the Component Update Tool should be launched from the menu Project->Update Components. This will provide the opportunity to select the version for each component instance that has multiple versions available. UARTTx_1 is the instance of interest in this example. Note that the Component Update Tool allows both upgrading and reverting to an older version if issues are found.
It also includes a link to the datasheet for the selected “Available Version”. The datasheet has a section that describes the changes made.
I’ve updated the library and made it available here: PSoC Sensei Library 01/27/2011.
We’ve added a new capability to our
Jan 19, 2011
In my post Creating Your Own Components I explained that there are 3 levels of component development:
At that point I had a set of 4 On-Demand Training classes (PSoC Creator 110 to 113) that explained the development of the first two component types. Now I'd like to point you to the latest On-Demand classes that are focused on datapath component development. Most of the digital components that Cypress provides in the standard library have been developed using datapaths and now the training is available to allow you to use the datapaths as well.
There are a couple of reasons that you might want to consider using a datapath in your own components:
Developing datapath based components will require learning the way that a datapath is configured and that's why I've put together these training classes at www.cypress.com/go/training:
Now I'll get working on some new components.
Dec 27, 2010
The PSoC Sensei Component Library now has the 7-bit down counter hardware called Count7 encapsulated into a component. The latest library is available here: PSoCSenseiLibrary122710.zip
This component uses some optional pins, so I'll use this component as an example to explain how that is implemented. There are several modes of operation for the Count7 and depending on the mode the enable (en) and load (load) signals may or may not be present.
This is implemented on the component by two parameters on the symbol. These parameters are passed to the hardware where they provide the parameters to the count7 primitive instance. The “Hardware” attribute of the parameter controls whether the parameter is passed to the Verilog implementation.
These parameters are also used to control the presence of the pins on the symbol. To control the presence of a pin select the pin in the symbol editor. Then right select and choose “Format Shape”. In this dialog the Visibility of the pin can be controlled using an expression that uses parameter values. A default value needs to also be provided. The pin is always present for the Verilog instance, so this becomes the value used when the pin is not present.
Next time you need a 7-bit or smaller down counter you have another implementation option with the Count7.
Dec 22, 2010
Each UDB has a datapath, control register, status register and 2 PLDs. An additional resource that is available is a count7. A count7 is 7-bit down counter that borrows some of the resources from the other parts of the UDB. Specifically the count7 uses the control register, it uses the mask register of the status register and if a routed load or routed enable is used, then the inputs that would be used by the status register are consumed. If neither the routed load nor enable are used, then a status register can still be used in the UDB, but the interrupt capability (statusi) is not available. That means that for the cost of a control register and sometimes a status register you can get the functionality of a 7-bit down counter.
The SimpleCount7Test project demonstrates the simple usage of the count7. This design instantiates a count7 in Verilog as follows:
The waveform shows the count sequence that is generated starting from power up.
CNT_START refers to the software enable bit for the count7. The most common mistake I see with new users of the count7 is forgetting to set the software enable. The count7 comes up disabled. Software must write the CNT_START to 1 in the Aux Control register in order to enable the counter. Refer to the main.c in the example projects. The first cycle after being enabled the Period register is loaded into the counter and it then begins to count down. Once it hits 0 the period is reloaded. The Terminal Count (TC) goes active one cycle after reaching 0. The TC signal is registered which is the reason for the one cycle delay from the 0 count.
The FullCount7Test project demonstrates more of the features of the count7. It is instantiates the instance in Verilog as follows:
In this design the load and enable signals are connected to the two mechanical buttons on the DVK. Those buttons are low when pressed, so the inverters on the schematic change the polarity so that pushing the buttons causes enable or load to occur.
The routed hardware enable is in addition to the CNT_START software enable. Both must be active in order for the counter to count. The counter counts down on each clock when the enable is high.
The routed hardware load will cause the counter to be reloaded with the period count value on any clock where load is high and enable is also high. Note that enable must be high in order for the load to occur.
Another note on the load signal is that the load signal when count is 0 will prevent the TC from going active in the next cycle.
That's all there is to using the count7 in your own Verilog component. When you just need a count7 in a schematic design and to provide examples of how to create APIs around the count7, my next post will be a count7 for the PSoC Sensei library that you can just drop into a schematic.
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