With a handful of PSoC3 resources and an external capacitor, a Voltage controlled oscillator can be created.

Pin "Cint" is configured as both Digital and Analog pin with a drive mode Open Drain drives low. When output of Comparator is High, IDAC output is connected to the pin.  When comparator output is Low, the pin shorts to Ground.

IDAC – configured as a source – charges an external capacitor connected to "Cint". When the capacitor voltage crosses input voltage Vin, comparator output becomes low (comparator is set for inverted logic) and discharges the capacitor. As capacitor voltage becomes zero, the comparator output becomes high and IDAC starts charging the capacitor. The cycle continues and we get an oscillator whose frequency is inversely proportional to Vin.  The circuit has excellent “Period vs. Vin” linearity.

For a given input voltage, the combination of IDAC value and external capacitor determines the maximum Period (1/f) of the output.  We know that when a capacitor is charged using a constant current, the time taken to charge to a known voltage is

t = C * V / I

For example, if the maximum period value is desired to be 500uS for an input voltage of 2.5V, for an IDAC value of 1uA, the value of C can be calculated:

C = (500uSec * 1uA) / 2.5V = 200pF

The comparator is synchronized to a clock.  The period of the clock should be long enough to discharge the capacitor.  Too high a clock frequency, the capacitor may not discharge completely.  Too low a clock frequency, the % of the "discharge time" to "charge time" will increase and will reduce the linearity.  The value of the clock will also depend on the value of the capacitor.  Higher value of capacitor will require a longer discharge time.

Selecting the right combination of IDAC, Capacitor and the SyncClock is an interesting exercise left to the user.

The project for the above can be found here.

In the recent FAE Conference held in the 3rd week of May 2010, I had a chance to attend a session on “Analog Signal Chain” taken by our Analog experts Dennis and Mark. They showed some really cool tricks using the PSoC3 analog. Some of this stuff was really amazing.

In a couple of my earlier posts, I had talked about doing higher resolution DACs using Parallel DACs and Dithering. This time, Mark showed us the trick to create four DAC outputs using a single DAC, the SC/CT blocks, an LUT and the DMA.

The four SC/CT blocks are configured as Track and Hold circuits whose inputs are connected to the VDAC8.  A four byte array in the RAM holds the values for the four DAC outputs. The DMA reads from this four byte array and writes to the DAC in sequence. An LUT component generates the trigger for the DMA and the Track and Hold circuits. The sequence goes like this.

DMA updates VDAC with the first value, LUT generates the strobe for the TrackAndHold1 and the output of the DAC is held on output1.
The LUT generates a trigger to the DMA which updates DAC with the second value. LUT generates a trigger to TrackAndHold2 and Output2 now has the 2nd DAC value.
This repeats for all the four DAC values and the cycle continues.

The refresh rate is chosen fast enough such that there is very little droop in the TrackAndHold outputs. Also, there is no CPU overhead as everything is taken care of by the DMA. The only overhead for the CPU is to update the RAM array with the desired DAC value. As the TrackAndHold has low output impedance, there is no need to buffer the outputs.

Coming soon is an Application Note on this cool trick.

After I published my video on Connecting Multiple Wired Hardware Bus in PSoC Creator, I received a feedback from PSoC Sensei that there are easier methods to get this done.  He even took the trouble to create a small video of screen capture showing how to do this and sent this to me.  Based on his feedback, here is an updated version of the video.

Thank you, PSoC Sensei!

When I was working on the project to test the High Resolution Dithered DAC, I had to connect two control registers to the input of a 2:1 8 bit wide mux and the output of this mux to the Data bus of the DAC.  After many failed attempts to create a bus connection, one of the PSoC3 geeks taught me how to do this in the PSoC Creator.  I created this video so that it may be useful to others who come across the same requirement.  Hope you enjoy the video.

An updated version of this video is available in this post.

A couple of weeks ago, I had written about a method to implement a High Resolution DAC using two 8 bit DACs.  Recently I had a very interesting discussion with one of my colleagues and a good friend, a young and brilliant guy named Kannan.  He showed me how to implement a high resolution Dithered DAC using a single 8 bit DAC, an 8 bit Mux, a couple of Control Registers and a PWM.  It is amazing what you can do with the PSoC 3 hardware.

Dithering is a widely used technique in Digital Processing where a noise is intentionally introduced into a system to increase the resolution of the system.  Say we have an 8 bit DAC with a full scale value of 255mV.  Each count of the DAC represents 1mV.  What if we wanted an output of 1.25mV from the DAC.  Switch the DAC output between 1mv and 2mV keeping the output at 2mV 25% of the time and 1mV 75% of the time, the average value of the output would be 1.25mV.  For an output of 1.5mV, the DAC output should be maintained at 2mV for 50% of the time and 1mV 50% of the time.

Now let us see how this method can be implemented using the PSoC 3 hardware to create a 10 bit DAC.

Place an 8 bit voltage DAC.  Select 1.020V (4mV / bit) as the range.  Set the Data_Source to “DAC Bus” and Strobe_Mode to “External”.  The output of the DAC can now be controlled using an 8 bit data bus and the output will be updated on the rising edge of the Strobe input.

Place a Multiplexer from the Digital >> Logic category.  Set number of input terminals to 2 and terminal width to 8.  The multiplexer can now switch between two 8 bit data buses.  Place two control registers from the Digital >> Registers category.  Set the number of outputs to 8.  Connect the 8 bit data bus of the Control registers to the input of the Multiplexer. 

Place a PWM, with a period of 3 and compare type set to “Less than”.  The output of the PWM now can be controlled to 0%, 25% and 75% duty cycle.  Connect the output of the PWM to the control input of the Mux.  Use the same clock of the PWM as a strobe to the DAC.  The hardware is now ready.

In firmware, write the Most Significant 8 bits of the 10 bit DAC value to the ControlRegister0 and one count higher value to ControlRegister1.  Use the Least Significant 2 bits to update the PWM’s pulse width.  Now, the PWM switches the input of the DAC between the two 8 bit Control Register values and the average output of the DAC would be our 10 bit DAC result.  Use an external Low Pass filter to remove the switching frequency.  As the switching frequency is at 125KHz, a simple RC filter will do the trick.  Below is the code.

void main()
{
   uint16 DacValue;
   VDAC8_Start();
   PwmMsb_Start();
   Amplifier_Start();
   for(;;)
   {
      DacMsbReg0_Write(DacValue >> 2);
      DacMsbReg1_Write((DacValue >> 2) + 1);
      PwmMsb_WriteCompare((uint8)(DacValue & 0x03));
   }
}

The range of the DAC now is 0 to 1020 counts; each count representing 1mV, subject to some offset and gain error inherent in the 8 bit DAC.

Quoting my brilliant friend “I bet this cannot be implemented with any other controller out there in the market!!”