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The PSoC Hacker Blog
Mar 23, 2014
PSoC has a single GPIO interrupt vector which is common for all the GPIO pins.  This poses some problems when interrupts are enabled on multiple GPIO pins.  Let us discuss the problems introduced by this architecture and techniques to address these problems.
 
The interrupt logic of a GPIO cell is shown in figure below.  
 
 
The PRTxICx registers set the type of interrupt (disabled, high, low and change from last read).  The corresponding PRTxIE bit enables or disables the interrupt for the GPIO.  When the interrupt is enabled in the PRTxIE register and if the interrupt condition as configured by PRTxICx occurs on the GPIO pin, the IRQ# line is asserted.
 
The IRQ# lines from all the GPIO cells are tied together.  This creates a wired OR setup for the active LOW IRQ signal.  The IRQ signal is considered edge sensitive for asserting and level sensitive for releasing the interrupt. i.e., the interrupt controller registers a GPIO interrupt when a falling edge is detected on the IRQ line, but will not register any interrupts till the IRQ line goes back to HIGH state.  This creates problems in detecting multiple interrupts occurring simultaneously.
 
For example, consider the scenario #1 shown in figure below.
 
 
GPIO#1 is configured for high level interrupt whereas GPIO#2 is configured for low level interrupt.  When GPIO#1 goes high, the IRQ line is asserted and the interrupt controller posts an interrupt.  While GPIO#1 is high asserting the IRQ line, GPIO#2 too goes low asserting the IRQ signal, and goes high de-asserting it before GPIO#1 de-asserts the IRQ.  As no change is registered on the IRQ line, the interrupt from GPIO#2 is not registered by the interrupt controller. 
 
Now consider another scenario #2 shown in figure below.
 
 
In this case, GPIO#1 asserts the IRQ line.  Before it de-asserts the IRQ line, GPIO#2 also asserts the IRQ line.  GPIO#2 continues to assert the IRQ line even after GPIO#1 de-asserts. As there is no state change on the IRQ line, the interrupt controller does not register the interrupt from GPIO#2.
 
Well. How do we address these scenarios?  Below are some techniques that can be used to overcome these situations.
 
1. As soon as a GPIO pin generates an interrupt, change the interrupt type of the GPIO (high to low or low to high).  This will immediately disable the GPIO from keeping the IRQ asserted.
2. Configure the interrupt mode to Change from Read .  When the interrupt is asserted, inside the ISR, read from the PRTxDR register and this will immediately de-assert the IRQ line.
3. To address extreme corner cases where another GPIO asserts the IRQ line before the interrupt type of the present GPIO is changed, keep a copy of all the pin states in a RAM variable.  Every time a GPIO interrupt is triggered, check the state of all the pins and compare this with the previous state stored in the RAM variable.  This way, all the pins that changed state can be detected.  Before exiting the ISR, update the RAM copy with the present state of the GPIO pins.
 
Apart from the above techniques, if you have free digital blocks or analog blocks left, you can also route the GPIO pin to a digital buffer and enable the interrupt of that digital block, or connect the GPIO to a comparator and enable the interrupt of the comparator bus.  This will provide dedicated interrupt vectors to the GPIOs.
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Tags: PSoC® 1
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Mar 20, 2014

Usually in battery operated applications, the microcontroller also measures the level of the battery and either displays the percentage of the battery left or generates an alarm when the battery level is getting low.  There are two methods to measure battery voltage.

Method #1: In microcontrollers that have an internal ADC reference, the straightforward approach is to use a potential divider and scale down VDD to the ADC s measurement range.  For example, if the internal VREF of the ADC is 1.024V, and we need to measure VDD which can vary from 3.0V to 4.2V (this is the range of a Lithium Ion battery), the following circuit may be used.

In the above circuit, R1 and R2 form a potential divider and would develop 1.024V when VDD equals 4.43V.  So, for a 12 bit ADC, VDD may be measured by the following equation.

VDD = (4.43/4095) * ADC Counts

 

Method #2: In microcontrollers that do not have an internal ADC reference, but use VDD as the reference, we need an external reference to measure VDD.

    

In the above circuit, an external reference of 1.2V is connected to the ADC input.  As the reference of the ADC is VDD, the ADC counts for VDD would always be 4095 counts.  So, the ADC counts while measuring the external reference would be proportional to VDD.  For a 12 bit ADC, VDD can now be calculated using following formula.

VDD = (1.2V * 4095) / ADC Counts

Both the above methods have a disadvantage that they require external components.  We can implement the same VDD measurement in PSoC4 without using any external components.  Let us see how.

Note: The resistor and zener combination in the schematic above is just a representation of an external reference voltage.

PSoC4 Implementation

The diagram below shows the block diagram of the ADC inside PSoC4.

 

        

The input to the SAR ADC can be directly from the SARMUX in Port2 or from the AMUXBUS that can connect any pin to the ADC.  The SARREF block generates the reference to the ADC.  Below picture shows the SARREF block.

  

The reference to the ADC can be one of three voltages 1.024V, VDD or VDD/2.  There is a bypass switch that brings out the output of the reference buffer to P1.7.  The intent of this bypass switch is to reduce noise on the VREF by connecting an external bypass capacitor.  We are going to use this bypass switch and Method #2 described earlier to measure VDD.

Following are the steps to measure VDD:

Connect an external bypass capacitor 1uF to P1[7].

Set the reference of ADC to VREF and enable the bypass switch.  Keep the bypass enabled for a short time, say 25ms. This charges the 1uF capacitor to 1.024V.

Disable the bypass switch. Now the capacitor holds the 1.024V (like a sample and hold circuit)

Change the reference of the ADC to VDD, connect P1[7] as input to the ADC and measure the voltage. 

VDD can then be calculated using the formula:

VDD = (1.024 * 2047) / ADC Counts P1[7]

The SAR ADC in PSoC4 is 12 bits. Then why am I using 2047 and not 4095 in the above equation?  With the ADC configured for single ended measurement, the effective resolution of the ADC becomes 11 bits and hence the full scale count of 2047.

Let us now take a look at the project.  Figure below shows the schematic of the project.

Place an OpAmp configured as a buffer.  Place an analog input pin and connect this pin to the input of the buffer.  Assign P1[7] to this pin.  Place an ADC and configure the ADC for a reference of VDDA (we will dynamically change this in code).  Select the Single Ended Negative Input to VSSA.

Following firmware will now take care of the VDD measurement.  The result is availabe in the variable "Vdd" in millivolts.

void main()
{
int16 Vref;
int16 Vdd;
uint32 SARControlReg;
 
/* Start the LCD, OpAmp and ADC */
OpAmp_Buffer_Start();
ADC_Start();
 
for(;;)
{
/* Set the reference to VBG and enable reference bypass */
SARControlReg = CY_GET_REG32(CYREG_SAR_CTRL);
SARControlReg &= ~0x000000F0;
SARControlReg |= 0x000000C0;
CY_SET_REG32(CYREG_SAR_CTRL, SARControlReg);
 
/* 25ms delay for reference capacitor to charge */
CyDelay(25);             
 
/* Set the reference to VDD and disable reference bypass */
SARControlReg = CY_GET_REG32(CYREG_SAR_CTRL);
SARControlReg &= ~0x000000F0;
SARControlReg |= 0x00000070;
CY_SET_REG32(CYREG_SAR_CTRL, SARControlReg);
 
/* Perform an ADC conversion */
ADC_StartConvert();
ADC_IsEndConversion(ADC_WAIT_FOR_RESULT);
Vref = ADC_GetResult16(0x00);
 
/* Calculate Vdd */
Vdd = (1024*2047)/Vref;
}
}
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Tags: PSoC® 4
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Oct 11, 2012

Here is a video that I created for Getting started with PSoC Designer 5.3. View it in 720p or 1080p for higher quality.

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Tags: PSoC® 1
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Oct 01, 2012

Here is a video I made on introduction to PSoC 1 architecture and design flow.

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Tags: PSoC® 1
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Sep 05, 2012

Here is a video I made for Getting Started debugging a PSoC1 project.  This is a two part series and in the first part, I have covered the hardware requirements.  The second part that covers the PSoC Designer part of the debugging will follow soon.

Application note "AN73212 - Debugging with PSoC1" provides all the information required to debug a PSoC1 project.

Happy Debugging!

Rating: (5/5) by 2 users
Tags: PSoC® 1
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