One of the most common questions I come across is “How do I measure a negative voltage using PSoC?”  For example, I have a +1V signal that I need to measure using PSoC ADC.  But the PSoC will not take any voltage below VSS.  How do I measure the negative portion of the input signal? 

The solution depends on the answer to two questions. 

Is the signal ground isolated from PSoC ground (VSS)? 
Is the signal AC or DC?

Signal Ground Isolated from PSoC Ground

If the signal ground is isolated from VSS of PSoC, then for both AC and DC input signals, the solution is simple and same.  Bring out AGND to an external pin and then feed the signal with respective to this AGND.

In the schematic above, the internal AGND is brought out on P0[5] using the Analog buffer and the signal is connected between this AGND and the PSoC input.  Set the reference of the PGA (if you are using a PGA to amplify the signal) to AGND and the DataFormat of the ADC to “Signed” and the PSoC is now ready to measure a –ve signal.
More about bringing out AGND to an external pin can be found in the below article.

Bring out AGND to an external pin

Signal Ground is Same as PSoC Ground – AC signal

If the signal ground is same as VSS, and if the input signal is AC, then the signal reference can be shifted from VSS to AGND by using a capacitor and a resistor.

In the above schematic, AGND is brought out to P0[5].  The signal to be measured is connected to the PSoC input through capacitor “C” and the PSoC input is biased to AGND by resistor “R”.  C and R form a high pass filter and hence should be selected in such a way that the input signal is passed without attenuation.  Set reference of the PGA to AGND and DataFormat of ADC to Signed.

Signal Ground is Same as PSoC Ground – DC Signal

When the input signal is DC and the signal ground is same as VSS, then the input can be shifted to AGND by biasing the input to VREFHI.

In the above circuit, the input signal is connected to the PSoC input through resistor R1, and the input of the PSoC is biased to VREFHI using R2.  VREFHI can be brought out to a pin the same way as AGND is brought out, either by using the RefMux user module, or by writing to the ACBxxCR2 register. 

With this circuit, the input signal will be lifted to AGND and attenuated by a factor of 2.  This method works for references that have VSS as REFLO, ie (Vbg + Vbg), (Vdd/2 + Vdd/2) and (1.6Vbg + 1.6Vbg). 

For example, for a reference of (Vbg + Vbg), the Analog Ground is at 1.3V and VREFHI is at 2.6V.  For a +1V input, following are the voltage levels on the input of PSoC for various input signal voltage levels.

From the above table, it is clear that the input signal gets shifted to 1.3V (AGND) and is attenuated by a factor of 2.  One side effect of this method is the difference between the shift created by the resistor network and the internal AGND will be amplified by the PGA.  But this can be compensated in firmware.

Depending on the type of input signal and isolation between signal and PSoC grounds, one of the above methods may be used to measure a –ve signal using PSoC.

Back to the blog world after a long period of inactivity. In the past few months, I have had a chance to work on a very interesting project for our CEO T.J. Rodgers.  He is donating 152 wine fermenters to the U.C Davis School of Enology and Viticulture.   A couple of articles that talk about the project: Blending Science With Wine, UC Davis claims world’s greenest winery

An important part of the fermenter is a temperature controller that controls the temperature of the fermenting grape juice – also known as “Must” – during the fermentation process.  The stainless steel drum that holds the ”must” is surrounded by a jacket through which cold or warm water is passed.  A PSoC is used to sense the temperature of the “must” using a thermistor, and based on the desired set point, controls the flow of cold or warm water through the jacket to maintain the temperature of the “must”.  The PSoC controls the water flow by operating a solenoid valve connected to the outlet port of the jacket. 

In this blog post, I am going to discuss the valve control section of the temperature controller.  This can be used in many other interesting applications like automatic garden irrigation, bathtub overflow control etc.

The primary design challenge was that the temperature controller was battery operated.  Because of this, a continuously on solenoid valve cannot be used.  The solution was a latching solenoid valve from Orbit.

This valve is used in commercial water sprinklers.  The valve has an inlet port and an outlet port for water.  A plunger opens or closes the valve.  This plunger is operated by two magnetic coils.  Energizing one of the coils with a 15V/20mS pulse opens the valve.  Once on, the valve latches and stays on without any further need for power.  Energizing the other coil with the same pulse closes the valve and the valve latches and stays closed.  The schematic of the valve control is shown below.
 

LT1303 is a charge pump, which is used to step up the 3.5V - 4.5V battery voltage to 15V and charge C6, a 2200uF capacitor.  J3 is a socket for the Orbit valve.  The common is connected to the +ve of the 2200uF capacitor.  The other two pins are connected to the drain of T1 and T2, N Channel MOSFETs.  Applying a pulse to the gate of these transistors will discharge the charge in capacitor through the corresponding coil.  Let us have the look at how the PSoC controls this circuit.

The PSoC controls the charge pump through the CH_PMP_SHDN and VB_FB signals.  CH_PMP_SHDN is a GPIO pin configured as StdCPU/Strong and turns on or off the charge pump.  VB_FB is the feedback signal used to sense the voltage on the 2200uF capacitor.  Figure below shows the PSoC Designer resource placement for the valve control.

 
A comparator is used to compare VB_FB with a fixed threshold generated by a DAC6.  The voltage on the 2200uF capacitor is derived by the formula.

Vout = Vref/10K * 160K

where
Vout = Voltage on the 2200uF
Vref = Comparator reference voltage

When the voltage across the 2200uF cross the desired output, the comparator goes high, and the PSoC turns off the charge pump and generates a 20mS pulse on gate of the respective MOSFET to turn On or Off the Orbit valve.

Following code is used to turn on the valve. 

    // Enable the Charge Pump
    CH_PMP_ENABLE;
   
    /* Set Analog reference power to SC On / Ref Med */
    ARF_CR |= 0x06;
   
    /* Start the CMP and DAC modules */
    CMP_Start(CMP_MEDPOWER);
    DAC_Start(DAC_MEDPOWER);
    DAC_WriteBlind(26);
   
    /* A small delay for the DAC and comparator to stabilize */
    DelayMs(5);
   
    /*     Wait for the comparator output to go high
        When comparator output becomes high, it means Vboost is around 18V */
    while(!(CMP_CR0 & 0x80));
   
    // Disable the Charge Pump
    CH_PMP_DISABLE;
   
    // Set the VALVE_ON GPIO
    VALVE_ON_Data_ADDR |= VALVE_ON_MASK;
   
    /* Switch off the CMP and DAC */
    CMP_Stop();
    DAC_Stop();
   
    /* Set analog reference power to all off */
    ARF_CR &= ~0x07;

    // 20mS Delay
    DelayMs(20);
   
    // Clear the VALVE_ON GPIO
    VALVE_ON_Data_ADDR &= ~VALVE_ON_MASK;

Enable the charge pump, switch on the comparator and DAC, wait for the comparator output to go high, disable the charge pump, turn off comparator and DAC and switch on the VALVE_ON GPIO for 20mS.  This will turn on T1 and discharge C6 through the On coil thus turning on the valve.  Similar code is used for turning off the valve where T2 is switched On.

Stay tuned for more interesting topics on the Fermenter!

With a handful of PSoC3 resources and an external capacitor, a Voltage controlled oscillator can be created.

Pin "Cint" is configured as both Digital and Analog pin with a drive mode Open Drain drives low. When output of Comparator is High, IDAC output is connected to the pin.  When comparator output is Low, the pin shorts to Ground.

IDAC – configured as a source – charges an external capacitor connected to "Cint". When the capacitor voltage crosses input voltage Vin, comparator output becomes low (comparator is set for inverted logic) and discharges the capacitor. As capacitor voltage becomes zero, the comparator output becomes high and IDAC starts charging the capacitor. The cycle continues and we get an oscillator whose frequency is inversely proportional to Vin.  The circuit has excellent “Period vs. Vin” linearity.

For a given input voltage, the combination of IDAC value and external capacitor determines the maximum Period (1/f) of the output.  We know that when a capacitor is charged using a constant current, the time taken to charge to a known voltage is

t = C * V / I

For example, if the maximum period value is desired to be 500uS for an input voltage of 2.5V, for an IDAC value of 1uA, the value of C can be calculated:

C = (500uSec * 1uA) / 2.5V = 200pF

The comparator is synchronized to a clock.  The period of the clock should be long enough to discharge the capacitor.  Too high a clock frequency, the capacitor may not discharge completely.  Too low a clock frequency, the % of the "discharge time" to "charge time" will increase and will reduce the linearity.  The value of the clock will also depend on the value of the capacitor.  Higher value of capacitor will require a longer discharge time.

Selecting the right combination of IDAC, Capacitor and the SyncClock is an interesting exercise left to the user.

The project for the above can be found here.

In the recent FAE Conference held in the 3rd week of May 2010, I had a chance to attend a session on “Analog Signal Chain” taken by our Analog experts Dennis and Mark. They showed some really cool tricks using the PSoC3 analog. Some of this stuff was really amazing.

In a couple of my earlier posts, I had talked about doing higher resolution DACs using Parallel DACs and Dithering. This time, Mark showed us the trick to create four DAC outputs using a single DAC, the SC/CT blocks, an LUT and the DMA.

The four SC/CT blocks are configured as Track and Hold circuits whose inputs are connected to the VDAC8.  A four byte array in the RAM holds the values for the four DAC outputs. The DMA reads from this four byte array and writes to the DAC in sequence. An LUT component generates the trigger for the DMA and the Track and Hold circuits. The sequence goes like this.

DMA updates VDAC with the first value, LUT generates the strobe for the TrackAndHold1 and the output of the DAC is held on output1.
The LUT generates a trigger to the DMA which updates DAC with the second value. LUT generates a trigger to TrackAndHold2 and Output2 now has the 2nd DAC value.
This repeats for all the four DAC values and the cycle continues.

The refresh rate is chosen fast enough such that there is very little droop in the TrackAndHold outputs. Also, there is no CPU overhead as everything is taken care of by the DMA. The only overhead for the CPU is to update the RAM array with the desired DAC value. As the TrackAndHold has low output impedance, there is no need to buffer the outputs.

Coming soon is an Application Note on this cool trick.

Last week end – this is my first visit to the US – I had a chance to visit the 17 Mile Drive in Monterey Bay.  My friend and colleague Palani took a great risk and agreed to teach me to drive on the US roads, especially the freeway. 

The Teacher and the Student

He taught me lane discipline, important road symbols, looking over shoulders before switching lanes, entering the freeway at 60mph (I would never dare do this in India) and many more.  I did throw him a few scares by driving on the left side of the road a couple of times (deserted roads of course) and once changing lane without looking behind my shoulder.  Thanks to his tutelage I have learnt the ropes and now I am able to drive in San Jose roads without getting honked at (just once in the past 5 days).

The Lone Cypress Tree

This is “The Lone Cypress Tree” which stands on a rock for more than 200 years (some web sites claim more than 250 years).  I learnt from a colleague Don that this tree which stands as a symbol of stability weathering time is the inspiration behind the Cypress Logo.
Here are some more interesting photos from this trip.

The majestic Brown Pelican in flight

This Beechey Ground Squirrel was quite bold and posed for me

A Western Gull resting on a rock