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Bridges - West Bridge® Controllers

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Results 1 - 13 of 13
Title Customer Rating Updated
AN47994 - Interfacing TI OMAPV1030 Processor to Cypress West Bridge® Antioch™

Not yet rated 		01/21/13
AN72419 - West Bridge® Benicia™ Hardware Design Guidelines and Schematic Checklist
AN72419 discusses the hardware design best practices and the device configuration for the West Bridge® Benicia™ device.
Not yet rated 		12/11/12
AN56835 - Interfacing West Bridge® Astoria to WirelessUSB™ LP
West Bridge® Astoria is a USB and mass storage peripheral controller that contains three main ports: processor interface (P-Port), mass storage support (S-Port), and USB interface (U-Port).
(5/5) by 1 user 		11/28/12
AN68914 - EZ-USB® FX3 I2C Boot Option

(5/5) by 2 users 		11/27/12
AN64465 - West Bridge® Integration to Android on OMAP Zoom II MDP: RNDIS, CDC-ECM, and Mass Storage Functions

Not yet rated 		08/14/12
AN49081 - Requirements for Input Clock to West Bridge® Devices
AN49081 addresses the requirements for the input clock to West Bridge® devices that includes Antioch™, Astoria™, and TX3LP18. The conversion of phase noise specifications into equivalent RMS jitter is also discussed.
Not yet rated 		08/14/12
AN47864 - Interfacing TI OMAPV1030 Processor to Astoria's Pseudo-NAND Processor Port

(5/5) by 1 user 		08/14/12
AN46860 - Schematic Review Checklist for West Bridge® Astoria™

Not yet rated 		08/14/12
AN46712 - Interfacing to the West Bridge® Astoria™ Pseudo-NAND Processor Port

Not yet rated 		08/14/12
AN34359 - PCB Layout Guidelines for West Bridge™ Generation A Peripheral Controllers in Wafer Level Chip Scale Package

Not yet rated 		08/14/12
AN13652 - Schematic Review Checklist for West Bridge® Antioch™

(3/5) by 1 user 		08/14/12
AN52970 - Windows Hardware Quality Labs (WHQL) Signing Procedure for Customer Modified Cypress USB Driver Files

(4.6/5) by 5 users 		07/10/12
AN48903 - External EEPROM Firmware Load for West Bridge® Astoria™

Not yet rated 		10/27/11
Results 1 - 13 of 13