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Title
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Customer Rating
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Updated
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Aligning byte enables for synchronous dual port
- If I connected a 32-bit processor to a 36-bit wide dual-port, how can I align the byte enables?
- Can I use the byte enables of the 18-bit wide dual-port if my system is only 16 bits?
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Not yet rated
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06/11/11 |
Migration from FLEX 72 to FLEX 72-E
- How to migrate from FLEx72 Migration to FLEx72-E ?
- What do the notes on page 2 of the datasheet mean?
- If I do not wish to use these features, what should I do with the pins?
- What do the pins labeled with a note do in the FLEx72-E?
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Not yet rated
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06/11/11 |
Partial access to Dual Port mailbox
Does writing or read only to the upper/lower byte (using LB# and UB#) of the mailbox trigger or clear the interrupt flag?
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Not yet rated
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06/11/11 |
Data valid period during two consecutive read cycles with the same address
During a flow-through read cycle, your datasheets specify that tCD1 after the rising edge of the read CLK, data is ready to be read. They also specify that the data will remain valid for tDC. My question is what would happen if you perform two flow-through read cycles with the same address consecutively? The datasheet shows a data valid period followed by unknown data followed by the data valid period for the following read. Does this apply to this case? Or will the same valid data from the first read remain on the data lines until the end of the second read cycle?
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Not yet rated
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06/11/11 |
Burst Counter Wrap-Around
- What happens when I use the burst counter and reach the very last memory location?
- Does the internal counter return to 0 when I reach the end of the memory array?
- If the burst counter wraps around to 0, will I be able to continuously read the data on every clock cycle or do I have to pause my reading operations?
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Not yet rated
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06/11/11 |
Timing and clock skew in synchronous Dual port during simultaneous read and write at same location
What does it mean to violate tCCS when one port is writing and the other reading from the same location?
How does the timing differ depending on whether it is the read or the write that happens slightly before the other?
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Not yet rated
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06/11/11 |
Bus Matching in CY7C09569V/CY7C09579V Dual-ports
How do I set up the bus-matching features on my dual-port?
How can I change the bus matching set-up after initial power-up?
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06/11/11 |
FullFlex - Variable Impedance Matching/Variable Impedance Sensing in Fullflex dual ports
What is Variable Impedance matching (VIM), Variable impedance Sensing (VIS)? How does it work, what are its effects and what are resistor tolerances?
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Not yet rated
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06/11/11 |
FullFlex - Echo clocks and their timing benefits
Explain Echo clocks for FullFlex Dual ports SRAM's? What are their timing benefits?
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06/11/11 |
Configuring pipelined vs. flow-through mode after power up
Can the Flowthrough/Pipeline mode be reconfigured after power-up for some Full flex dual port SRAM's?
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Not yet rated
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06/11/11 |
FullFlex - Power sequencing for the Fullflex
How is Power Sequencing done for the Fullflex Dual Ports?
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06/10/11 |
CY7C0852V BSDL and JTAG
CY7C0852V BSDL and JTAG Questions: - What is wrong with the Pause-DR state? - How do you prevent going into the Pause-DR state? - What happens during JTAG testing when I enter Pause DR? - What happens to the CY7C0852V JTAG Chain in PAUSE-DR State?
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Not yet rated
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06/10/11 |
Stand-by Power Consumption of the CY7C0853V
What is the ISB (stand-by current) value for the CY7C0853V?
How can I save power on the 9M dual-port?
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Not yet rated
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06/10/11 |
Programming Failure using ICE Cube
I am trying to program my enCoRe II device in system through a USB cable. I am using the ICE Cube, yellow ISSP cable and 5-pin to USB adapter. I get an error message on my PSoC Programmer user window that says, Programming succeeded, verify failed; sometimes it fails to Acquire device. How can I resolve this?
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Not yet rated
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06/10/11 |
ESD Protection of USB 2.0 Device Inputs
ESD protection required of modern testing methods.
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06/10/11 |
INT Line Behavior
What happens if an interrupt from any other source occurs after the read register command has been issued and before the data is available on FD [7:0]?
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Not yet rated
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06/10/11 |
Typical System Transfer Rate for an SX2 Device
Can the SX2 give a system throughput of 20-30MB/s in bulk mode? If so, how should the device be configured?
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06/10/11 |
CY7C68001-Ready Signal
Would it be better to check the rising edge for Ready rather then doing a level sensitive check?
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06/10/11 |
SX2 Endpoint Register Default Values
After enumeration, do all the registers in SX2 have the default values shown in the SX2 Register Summary of the datasheet?
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06/10/11 |
Buffering Interrupts.
The datasheet states that once the external master initiates a read request, all interrupts are buffered and the next interrupt from the SX2 is exclusively meant for the availability of the data from the read register request. When the external master has initiated a read request, and the SX2 triggers an interrupt ,interrupt status byte is seen instead of the read register request. Once the interrupt is cleared the next interrupt triggered has the value of the read request. So,when does the interrupts actually begin to get buffered ?
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06/10/11 |
Power supply decoupling required for HOTLink products
What special power supply decoupling is required for HOTLink products?
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06/10/11 |
Problems Writing Short Packets
I've already been able to do a bulk IN transfer using the FX processor as an external master (which will be eventually replaced by a DSP), but I still have the following problem: I'm trying to write a short byte array to EP6 (less than 512, which is the default). I'm using the register version of the PKTEND signal (e.g. writeregister(0x20, 0x04)), but it does not seem to commit the FIFO content to USB. How should this be done? I have successfully received data using the EZ-USB Control Panel writing 512 bytes to EP6 (from the perpheral), and doing a bulk read with length=512. Changing the bulk read length to anything else makes the communication fail.
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Not yet rated
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06/10/11 |
SX2 as a Universal Serial Bus Host.
Can the CY7C68001 be used with a MPC860 as a host in a USB network? If not, what is the alternative device for this application. If it can, is there a special configuration to set it up as the HOST or peripheral?
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Not yet rated
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06/10/11 |
Errors during UDMA data transfers in CY4611B
How does CY4611B handles CRC and parity errors during UDMA data transfers to ATA and ATAPI devices?
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Not yet rated
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06/10/11 |
Detecting ATA/ATAPI device on 40-pin ATA connector using CY4611B Firmware
In Cy4611B reference design how does the firmware detect if the attached device on 40-pin ATA Bus connector is ATA or ATAPI type?
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Not yet rated
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06/10/11 |
Relationships between TXCLK, RXCLK and REFCLK for the CY7C924ADX in asynchronous mode
What is the relationships between TXCLK, RXCLK and REFCLK for the CY7C924ADX in asynchronous mode?
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Not yet rated
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06/10/11 |
Framework files for FX1/FX2LP.
Where can I find the framework files of FX1/FX2LP?
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06/10/11 |
Avoiding “Found New Hardware Wizard” popup window in Windows
How to avoid “Found New Hardware Wizard” popup window in Windows when connecting the USB device?
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06/10/11 |
Enumerating SX2 in FULL Speed mode
How can I force the SX2 to enumerate in full speed mode only?
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06/10/11 |
Are the receiver discard policies affected when the FIFO's are bypassed in the CY7C924ADX?
Are the receiver discard policies affected when the FIFO's are bypassed in the CY7C924ADX?
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Not yet rated
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06/10/11 |
FX2LP is not enumerating when vend_ax.hex is downloaded into it. Why?
When I download vend_Ax firmware to FX2LP, it does not renumerate with the VID/PID that is specified in the dscr.a51 unlike the other code examples. Why?
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Not yet rated
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06/10/11 |
Reliable Enumeration of CY7C656xx Hub with Reset Consideration
What kind of situation CY7C656xx does not enumerate with the default descriptor?
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Not yet rated
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06/10/11 |
SX2 Crystal Oscillator Input
While using CY7C68001, if a 24MHz clock is already in the system, can it just be routed directly to the XTALIN pin, and leave the XTALOUT pin unconnected?
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Not yet rated
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06/10/11 |
Reset Signal High Duration for the CY7C68001 EZ-USB SX2
Does it matter how long the reset line is hold at high before going to reset?
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Not yet rated
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06/10/11 |
CY7C68001 EZ-USB SX2 INT# Pin Behavior for Multiple Interrupts.
The EZ-USB SX2 is capable of buffering multiple interrupts and INT# should be asserted if there is one or more pending interrupts. Must multiple interrupts be captured by an edge-triggered or level-triggered interrupt pin on the external master? For example, when there are two pending interrupts, reading the interrupt status byte clears the first interrupt. However, there is still one more pending interrupt, so the INT# line should be asserted again.
INT# ___/ \__
(1) (2)
INT# ______
(1) (2)
Which waveform is correct?
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Not yet rated
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06/10/11 |
Flushing the SX2 Read/Write FIFO
Should the SX2 FIFO be flushed before read/write?
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Not yet rated
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06/10/11 |
The way SX2 Clears the Status of the FLAGS and Other Interrupts.
How does SX2 clear the status of the FLAGS and other interrupts?
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Not yet rated
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06/10/11 |
Handling of USB bus reset by External master interfaced to SX2
How does the external master handle the case where SX2 receives a USB bus reset?
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Not yet rated
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06/10/11 |
External master and Data in SX2 FIFO
How does the external master determine if there's data in the SX2 FIFO to be read?
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Not yet rated
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06/10/11 |
SX2 Current Consumption
How much current does the SX2 consume in the unconfigured state (until enumeration is completed)?
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Not yet rated
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06/09/11 |
Connecting SX2 to both USB 1.1 and USB 2.0
Is it possible to connect the SX2 to USB 1.1 and 2.0 host controllers or only to USB 2.0 host controllers?
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Not yet rated
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06/09/11 |
Renumeration process in SX2 .
How is renumeration procedure possible if firmware cannot be uploaded to the SX2?
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Not yet rated
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06/09/11 |
Post-enumeration Initialization Steps -- SX2
What are the typical initialization steps the external processor needs to take after SX2 enumerates?
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Not yet rated
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06/09/11 |
Physical Interface and CPU Responsibilities for the SX2
What physical interface is presented to the external master or CPU from the EZ-USB SX2? What is the external master or CPU responsible for?
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Not yet rated
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06/09/11 |
Chip Select CS# Pin of SX2
What is the functionality of CS# of SX2 (CY7C68001)?
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Not yet rated
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06/09/11 |
Asynchronous FIFO Reads in the SX2
Is there an efficient way to learn how many bytes can be read from an OUT FIFO without checking the EmptyFlag after each byte read?
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Not yet rated
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06/09/11 |
Using SX2 as the clock source.
Can the SX2 be used to clock an external device? If so, what are the steps?
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Not yet rated
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06/09/11 |
SX2 Processor.
Does the SX2 have a processor (8051 ) like the FX2? If so, how is it different from the FX2?
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Not yet rated
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06/09/11 |
TCLK when TAP controller disable
To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. If tie high is the same, pull up, just not leave it float.
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Not yet rated
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06/09/11 |
Difference in version Standard, L and LL
What are the differences between the Standard, L version and LL version?
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Not yet rated
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06/09/11 |