|
Title
|
Customer Rating
|
Updated
|
Minimum PWM frequency in System level design
What minimum PWM frequency can be configured in System level design?
|
Not yet rated
|
06/13/11 |
Manually uninstalling PSoC Programmer / any other programs Cypress Software
How do I manually uninstall Cypress Software tools?
|
(3.5/5) by 2
users
|
06/13/11 |
What is the Best Way to Debug GPIF Applications?
What is the best way to debug my GPIF application?
|
Not yet rated
|
06/13/11 |
1-Wire Communication - Pull Up Resistor
Is an external pull up resistor required in 1-wire communication?
|
Not yet rated
|
06/13/11 |
CSD Parasitic Capacitance Calculator
How can I find the Parasitic Capacitance of my sensor from the raw counts? I am using CY8C21x34.
|
Not yet rated
|
06/13/11 |
Operating EZI2C in PSoC at lower than 50KHz frequency
I want to operate PSoC EZI2C as a slave in I2C communication. The I2C master clock frequency is 40KHz, but in designer the options available for CLK are 50KHz, 100KHz and 400KHz. Can PSoC respond to 40KHz ?
|
Not yet rated
|
06/13/11 |
SLRD/SLWR Pins During GPIF Mode of FX2LP
During GPIF burst transaction, is the GPIF in control of the SLWR, SLOE signals internally? Do I need to tie the appropriate CTLx output signals to these signals?
|
Not yet rated
|
06/13/11 |
EZ-USB FX2 GPIF Reference Materials
Are there any reference materials for the usage of EZ-USB FX2LP (CY7C68013A) GPIF engine?
|
Not yet rated
|
06/13/11 |
Current Status of the READYx Pins for the CY7C68013
Is it possible to read the current pin status of the GPIF ready lines through firmware?
|
Not yet rated
|
06/13/11 |
Restrictions/Limitations on using FX2LP IFCLK
Are there any concerns/restrictions/limitations on using IFCLK?
|
Not yet rated
|
06/12/11 |
WinCE Version For CyUSB.sys
Does Cypress provide a version of CyUSB.sys that is compatible with the WinCE OS?
|
Not yet rated
|
06/12/11 |
Can't Acquire Device - Error while Programming PSoC1
How do I correct the error message "Can't acquire device?"
|
Not yet rated
|
06/12/11 |
Enable MAC in Compiler Does Not Work
I cannot get the enable MAC to work.
|
Not yet rated
|
06/12/11 |
Build error - LMM info: 'Interrupt RAM' uses too many bytes
When I try to compile my project in PSoC Designer, I get the message:
Build error. LMM info: 'Interrupt RAM' uses 39 bytes in page 0.
and my project does not compile.
What do I need to do to make this work correctly?
|
Not yet rated
|
06/12/11 |
Accidental Modification of I/O Pins in PSoC1
I am unable to modify the state of a PSoC pin using instructions like PRTxDR |= 0x01, PRTxDR &= ~0x01. What am I doing wrong?
|
Not yet rated
|
06/12/11 |
DAC8 as Reference to a PGA
I am using the output of a DAC8 as reference to a PGA, but it does not work. What could be the reason?
|
(4/5) by 1
user
|
06/12/11 |
Difference between Factory Programmable and Field Programmable devices
What is the difference between Factory Programmable and Field Programmable devices?
|
Not yet rated
|
06/12/11 |
Change the "Select" type for pins in PSoC Designer firmware
How can I switch between "StdCPU" to "Global In" or "Global Out" bus within firmware?
|
Not yet rated
|
06/12/11 |
Drive strength differences between GPIO and SIO pins in PSoC 3/5
What are the differences in drive strength between GPIO and SIO pins in PSoC 3/5?
|
Not yet rated
|
06/12/11 |
Instruction executed after PSoC 3/5 wakes from Sleep/Hibernate mode
What instruction will be executed first when PSoC 3/5 wakes up from sleep/hibernate mode?
|
Not yet rated
|
06/12/11 |
Skipping generation of APIs of a component in PSoC Creator
Is there a way so that I can stop generating APIs for the components for which I do not want to use them?
|
Not yet rated
|
06/12/11 |
"No Kits or Solutions Found" error message while opening PSoC Creator
In the start page of PSoC Creator I am getting "No Kits or Solutions Found". How to solve this?
|
Not yet rated
|
06/12/11 |
Available PSoC 3 pin packages
What are the available PSoC 3 pin packages?
|
Not yet rated
|
06/12/11 |
Selecting a PSoC 3 part number based on requirements in Cypress Website
How to select a specific PSoC 3 part number based on my requirements in Cypress Website?
|
Not yet rated
|
06/12/11 |
Difference between XRES and configurable XRES in PSoC 3/5
What is the difference between XRES and configurable XRES (P1[2]) in PSoC 3/5?
|
Not yet rated
|
06/12/11 |
USBFS Not Appearing as Bootloader I/O in PSoC Creator
My USBFS component does not appear as the Bootloader I/O component in the Systems tab of design wide resources in PSoC Creator. How to solve this?
|
Not yet rated
|
06/12/11 |
Inverting the display of characters on 16x2 character LCD in PSoC Creator design
How to Display inverse of characters (i.e. to toggle dots which are On to Off and visa-versa) on 16x2 character LCD interfaced with PSoc 3/5 using PSoC Creator?
|
Not yet rated
|
06/12/11 |
Format of .cyacd file relating to PSoC 3/5 bootloaders
What is the format of bootloadable file ( *.cyacd ) created by PSoC 3/5 Bootloaders?
|
Not yet rated
|
06/12/11 |
Avoiding regeneration of source files in PSoC Creator
I do not want project’s configuration and source files to update. Is there a way to avoid creator to regenerate the source file on build?
|
Not yet rated
|
06/12/11 |
Migrating project from CY8CKIT-001 to CY8CKIT-030 or CY8CKIT-050
How do we make example project designed to work on CY8CKIT-001 to work with CY8CKIT-030 or CY8CKIT-050?
|
Not yet rated
|
06/12/11 |
Number of DelSig ADCs available in a PSoC 3/5 project
In PSoC 3/5 devices how many DelSig ADCs can be placed on a single chip?
|
Not yet rated
|
06/12/11 |
Avoiding changes in the source file to get overwritten in PSoC Creator
Whenever I modify the code in component’s generated source file, it gets removed whenever project is built in PSoC Creator. How to make modification to retain after build?
|
Not yet rated
|
06/12/11 |
Selecting the inductor value for Boost Regulator section of PSoC 3/5
How to select the right value of Inductor for the Boost Regulator section of PSoC 3/5?
|
Not yet rated
|
06/12/11 |
Connecting multiple interrupt sources on the same port of PSoC 3/5
Why can't I connect multiple interrupts on the same port? i.e., If I connect an ISR to pin P0[3], I'm not able to connect another ISR to pin P0[4].
|
Not yet rated
|
06/11/11 |
FIFOs vs Dual-ports
When is a FIFO used instead of a dual port? How do I select between a FIFO and dual-port for my application?
|
(3/5) by 1
user
|
06/11/11 |
Aggregate bandwidth and throughput of synchronous dual-ports
- How do you calculate bandwidth with dual-ports?
- What is the throughput of a particular dual-port?
|
Not yet rated
|
06/11/11 |
Using multiple devices to create a wider data path for synchronous dual port SRAM's
How can multiple dual-port devices be combined to create a wider data path?
Can I width cascade multiple dual-ports?
How would I set up the dual-port for width expansion?
|
Not yet rated
|
06/11/11 |
Depth and width expansion affect on board-level timing
How does memory depth and width expansion affect board-level timing?
|
(5/5) by 1
user
|
06/11/11 |
CY7C08xxV Read Cycle Latency
- Why is there no FT/PL pin in some of the synchronous dual-ports?
- What is the latency associated with read operations?
|
Not yet rated
|
06/11/11 |
Battery backed solutions for CY7C08xxV dual-ports
Why is the standby current rating (Isb) on these 2Mb (CY7C0851V) and 4Mb (CY7C0852V) dual-ports so high compared to the 1Mb devices? I would expect the difference in Isb to be fairly linear, but it is, in fact, several orders of magnitude greater. (10 mA vs. 10-50uA).
The complication comes in looking for a battery backup switcher. I've found none of these power monitors can handle >150uA of standby current. Does Cypress have an battery backed solution available for these high-density dual-ports?
|
Not yet rated
|
06/11/11 |
Simultaneous access in synchronous dual-ports
- Can I write to the dual-port at the same time from both ports?
- What happens when I read and write to the same location at the same time?
- What happens if I read from the same location at the same time?
- If both ports are running off the same clock how may clock cycles after I write can I initiate a read from the same address?
|
(4/5) by 1
user
|
06/11/11 |
Read-Back of Internal Address Counters for synchronous dual port SRAM's
- How can one see the current state of the internal counter?
- Is there a way to check the state the burst counter?
- Is address readback different for the CY7C08x1V / CY7C08x2V devices?
|
Not yet rated
|
06/11/11 |
Unused OE# and CE1 Pins
If I am not going to use these pins, what should I do with them?
|
Not yet rated
|
06/11/11 |
VSS vs. VSSQ for synchronous dual port SRAM's
What is the difference between VSSQ versus VSS in the datasheet?
|
Not yet rated
|
06/11/11 |
Burst Counter Operation and chip disabled for synchronous dual port SRAM's
If I do a read or write of a number of words and I use the internal counter (ie load the counter start address on the first word and then count after that), but I only give a CE (chip enable) every other clock; will I read data from consecutive address locations every other clock?
An example: For a burst read -- first clock load counter, second clock do nothing, third clock give chip enable and read first data, fourth clock do nothing, fifth clock give chip enable and read second data (next one in memory after first), sixth clock do nothing, seventh clock give chip enable and read third data, etc. Note that output enable and counter enable will always be active. Could you confirm this for me?
|
(5/5) by 1
user
|
06/11/11 |
Read and Write with Single Internal Counter for Synchronous Dual port SRAM's
What happens if we write on one clock cycle with ADS#, CE# and CNTEN# all low (i.e. load the address counter) and then, on the next cycle we read without ADS# but with CNTEN# (i.e. increment the counter). Will the address we read from be one higher than the one we loaded in the first cycle?
|
Not yet rated
|
06/11/11 |
Timing relationship of OE# to the dual-port
What is the timing relationship between OE# and CE# in synchronous Dual Ports? - How is the output enable signal connected to the clocks?
|
Not yet rated
|
06/11/11 |
Internal Power-On Reset (POR) Circuitry in Synchronous Dual-Ports
Do synchronous dual-ports have internal power on reset circuitry?
|
Not yet rated
|
06/11/11 |
CE not present in some Dual port SRAM's E.g CY7C0853V
- How do I enable and disable this dual-port since there are no Chip Enable (CE#) pins?
- If I have R/W# tied low on one side (always writing), how can I stop it when I need to?
|
Not yet rated
|
06/11/11 |
Data hold time
Data that is read out of a synchronous dual-port holds valid for a minimum period of "tDC". What is the maximum value?
How long will the data read out (Qn) be available on the data lines after the clock edge?
|
Not yet rated
|
06/11/11 |