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Title
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Customer Rating
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Updated
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TetraHub during RESET
What happens on resetting the TetraHub using the RESET# pin? Does the TetraHub re-enumerate? What states are the I/O pins? What state are the SPI_CS, SPI_SD and SPI_SCK in during reset? Is the EEPROM queried again on a reset?
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Not yet rated
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06/15/11 |
MBR2044 GPO's Drive modes and Logic levels
In CY8CMBR2044, what will be the Drive modes and Logic levels of GPOs under different operating modes?
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Not yet rated
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06/13/11 |
HOTLink II Three Level Control Inputs
Can the 3-Level select static control inputs be controlled by an FPGA/CPLD output?
(For CYP(V)15G0401DXB, CYP(V)15G0402DXB, CYP(V)15G0201DXB, and CYP(V)15G0101DXB).
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Not yet rated
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06/13/11 |
Switching between Serial Differential Inputs
- How long does it take for HOTLInk II receiver to switch between the serial differential inputs from IN1(+/-) to IN2(+/-)
- How long does it take for HOTLInk II receiver to switch between the serial differential inputs from IN1(+/-) to IN2(+/-)
- IN1(+/-) is coming from an external link. OUT2(+/-) loop back's to IN2(+/-). Two channels have the same freq. Before the external link is established, we select IN2. We have plenty of time for the receiver to lock in IN2. When the external link on IN1 becomes OK, we switch the receiver to IN1. How long does it take for the clock recovery to lock in? Does it still take 376K UI?
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Not yet rated
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06/13/11 |
Considerations in Interfacing HOTLink II to Fiber Optic Module
What are the considerations in Interfacing HOTLink II to Fiber Optic Module? How can I interface a SFP fiber optic module with HOTLink II?
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Not yet rated
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06/13/11 |
Receive Status Bits in HOTLink II
What is the purpose of receive status bits in HOTLink II? What is the function of priority in table 20 of the data sheet of CYP15G0401DXB? What are the different modes of status reporting?
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Not yet rated
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06/13/11 |
State of the RXSC/D* signal while VLTN is asserted for the CY7C9689A
What is the state of the RXSC/D* signal while VLTN is asserted for the CY7C9689A?
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Not yet rated
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06/13/11 |
Significance of HOTLink claim of requiring no external PLL components?
What is the significance of the HOTLink claim of requiring no external PLL components?
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Not yet rated
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06/13/11 |
Power consumption of the SMPTE 259M Scrambler/Controller and Descrambler/Framer-Controller
What is the typical power consumption of the SMPTE 259M Scrambler/Controller and Descrambler/Framer-Controller?
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Not yet rated
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06/13/11 |
Power (VDDA & VDD) and ground (VSSA & VSS) pins on the CY7C924ADX
What needs to be done with the power (VDDA & VDD) and ground (VSSA & VSS) pins on the CY7C924ADX?
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Not yet rated
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06/13/11 |
Configuration for connecting the HOTLink Transmitter/Receiver power and ground pins
What is the optimum configuration for connecting the HOTLink Transmitter/Receiver power and ground pins?
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Not yet rated
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06/13/11 |
Character Rate vs Byte Rate
Explanation of what character rate vs byte rate means?
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Not yet rated
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06/13/11 |
Built-In Selt-Test (BIST) and why should I use it?
What is Built-In Selt-Test (BIST) and why should I use it?
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Not yet rated
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06/13/11 |
Asynchronous vs Synchronous(Clocked) FIFOs
- What is the difference between clocked and synchronous FIFO's?
- What different types of FIFO's are there?
- Why should one prefer one type over another?
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Not yet rated
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06/13/11 |
Signal Overshoot / Undershoot
- How does signal overshoot affect FIFO operation?
- How does one fix overshoot/undershoot problems on the board?
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Not yet rated
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06/13/11 |
Cypress FIFO Architecture
- How is the FIFO made?
- Is the FIFO memory volatile or non-volatile?
- Is the FIFO memory static or dynamic?
- What is the architecture of Cypress FIFOs?
- Are Cypress FIFOs bubble-through FIFOs?
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Not yet rated
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06/13/11 |
General FIFO - Tri-stated signal connected to data inputs
What will happen if we have a tri-state output connected to the input of the FIFO? We are always driving the clock and control inputs; it is only the data inputs that will be receiving a tri-stated floating signal.
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Not yet rated
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06/13/11 |
External Master Reset of all Cypress FIFO's
- Is there a built-in reset in Cypress FIFO's?
- Is there POR circuitry in Cypress FIFO's?
- Do I need to reset the FIFO on power up?
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Not yet rated
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06/13/11 |
Master Reset problems
- What all things can affect Master Reset?
- Even after following timing specifications for Master Reset, it is not working , why ?
- Will noise on the signal lines affect the functionality of the device.
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Not yet rated
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06/13/11 |
Unidirectional vs. Bidirectional FIFOs
What is the difference between unidirectional and bidirectional FIFO's? Why would I use a bidirectional FIFO? How is memory shared in a bidirectional FIFO?
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Not yet rated
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06/13/11 |
Using /FF as a Half Full flag in depth cascaded FIFO's
If cascading two FIFO's in depth, can the full flag (/FF) of the first FIFO be used as the half full flag for both FIFO's?
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Not yet rated
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06/13/11 |
Replacing asynchronous FIFO's with synchronous FIFO's
- What design considerations are there when converting from an asynchronous FIFO to a synchronous one?
- What is different about designing with synchronous FIFOs?
- Can you operate a synchronous FIFO as an asynchronous one?
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Not yet rated
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06/13/11 |
Compiler for CY3650
Does a .rom file produced by a compiler work correctly on the CY3650 (or CY3651)?
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Not yet rated
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06/13/11 |
Requirement of Pull-up resistors on SCL and SDA lines when unsed
Is it required to connect pull-up and pull-down resistor on SCL and SDA lines when a device is not connected?
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Not yet rated
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06/13/11 |
Using GPIF pins ( RDY / CTL pins) for GPIO functionality in FX1 / FX2 / FX2LP
Can the GPIF RDYx and CTLx pins be used as generic input and output ports controlled directly by the 8051 when using the part in GPIF mode?? Specifically, can I use the GPIFREADYSTAT registers to sample the states of the RDYx pins, and the GPIFIDLECTL register to control the states of the CTLx output pins?
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Not yet rated
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06/13/11 |
CY3650 Development Kit Contents
What is included in the CY3650 Development Kit?
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Not yet rated
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06/13/11 |
Maximum Throughput Using FX2 (CY7C68013) GPIF Interface
What is the maximum sustainable transfer rate the FX2LP can obtain in GPIF transfer mode?
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Not yet rated
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06/13/11 |
Using RDY0 / RDY1 lines as GPIO in FX1/FX2/FX2LP
Can the GPIF's RDY0 pin can be used as a normal GPIO?
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Not yet rated
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06/13/11 |
Programming CY7C630xx/631xx using CY3650
Can the CY7C630xx/631xx parts be programmed with the CY3650?
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Not yet rated
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06/13/11 |
GPIFTC [B3:B0] Chip Revision - CY7C68013
In which chip revision was the GPIF transaction counter updated from 16 bits to the new 32-bit GPIFTC[B3:B0]?
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Not yet rated
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06/13/11 |
GPIO pins supported by CY7C68320/21.
How many GPIO pins does the CY7C68320/21 support?
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Not yet rated
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06/13/11 |
CY7C68300 / CY7C68300A - EZ-USB AT2 Must be Powered Before Attached Drive
Should CY7C68300 / CY7C68300A - EZ-USB AT2 be Powered Before Attached Drive?
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Not yet rated
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06/13/11 |
Suspend current specifications on the CY7C65640
Does the suspend current specifications on the CY7C65640 (100uA) include the current through the D+ resistor? What is the current flowing thru the internal D+ resistor during suspend?
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Not yet rated
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06/13/11 |
Unable to download the firmware (the .rom file) onto CY3650
I can't download the my firmware (the .rom file) onto my CY3650. When I download the file "test.rom", Why does the PC pop up a message saying "cmdDnldDnld_Click: DownLoad of test.rom ended before all valid characters were loaded into Program RAM. Stopped at Program RAM Address1"?
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Not yet rated
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06/13/11 |
CY3650 Setup
What are the step-by-step instructions to run firmware on CY3650?
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Not yet rated
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06/13/11 |
Setting up CY3650 CY3651 or CY3652
How do I set up the CY3650 CY3651 or CY3652?
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Not yet rated
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06/13/11 |
CYDB software for CY3650 (or CY3651, CY3652)
Can I run the CY3650 (or CY3651, CY3652) on the new CYDB software?
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Not yet rated
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06/13/11 |
State of TetraHub PWR# pins
What is the state of the PWR# pins when the hub is in a disconnected state from the host (BUSPOWER pin low) and the hub being a self powered device, is still in a powered state? Are these output pins still driven low or are they floating?
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Not yet rated
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06/13/11 |
CY7C68300 / CY7C68300A - CH8Ck Test Software from PIMC Reports Failures with the EZ-USB AT2
What are the invalid host behaviors when running Ch8Ck software?
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Not yet rated
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06/13/11 |
CY7C68300 / CY7C68300A -- Maximum Capacity of Hard Drive that the EZ-USB AT2 can Support
What is the maximum capacity of harddrive that the EZ-USB AT2 can handle?
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Not yet rated
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06/13/11 |
I just purchased a CY3652C Development kit and it fails the self-test program. The Device Manager shows UNKNOWN device.
I just purchased a CY3652C Development kit and it fails the self-test program. The Device Manager shows UNKNOWN device.
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Not yet rated
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06/13/11 |
Device manager sees attached device as 'Unknown Device'
When I run my firmware on the CY3650, under the Device Manager why does the host see my device as an 'Unknown Device'?
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Not yet rated
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06/13/11 |
Driver for the CY3650 DVK
When USB cable is plugged into the CY3650 board, the host sees it as an "Unknown Device". USB "selftest" is not seen. What is the driver for the CY3650? How to know if the development board is functioning correctly?
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Not yet rated
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06/13/11 |
Byte 7 of the EEPROM for a 0xD2 load.
How is byte 7 of the EEPROM interpreted? What is the purpose of the Enable Overcurrent timer and Disable Overcurrent Timer? What is the difference between these two parameters and how are they used?
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Not yet rated
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06/13/11 |
Is the TetraHub device USB compliant?
Is the TetraHub device USB compliant?
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Not yet rated
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06/13/11 |
Can the TetraHub interface with a small (1K/2K) EEPROM?
The reference design CY4602 of TetraHub USB Hub uses a 4K EEPROM. Can the TetraHub interface with a smaller (1K/2K) EEPROM?
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Not yet rated
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06/13/11 |
Are USB Hub drivers standard so that the user need not write a specific USB Hub class driver?
Are USB Hub drivers standard so that the user need not write a specific USB Hub class driver? The OS is Windows 2000 and XP.
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Not yet rated
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06/13/11 |
Buffer per TT?
While running the WHQL test on my TetraHub Device, the test asks for the buffer size per TT. What should I enter?
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Not yet rated
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06/13/11 |
TetraHub WHQL Certification
Is the TetraHub WHQL Certified?
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Not yet rated
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06/13/11 |
External Clock in PSoC Designer 5.0 SP5 does not work.
When System clock is selected as P1[4] in PD5.0 SP5, PSoC does not work. What is the problem and how do I make this working?
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(4.5/5) by 2
users
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06/13/11 |