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Title
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Customer Rating
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Updated
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Different Register Values EPxFIFOFLGS vs. EPxxFIFOFLAGS (FX2)
What is the difference (if any) between the value of the Flag bits in the EPxFIFOFLGS, EPxxFIFOFLGS and EP2468STAT registers?
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Not yet rated
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06/17/11 |
Slave FIFO Mode Synchronous Burst Read/Write with the CY7C68013 (FX2)
Does the FX2 device support synchronous burst read/write in slave FIFO mode? In the FX2 Technical Reference Manual, I am unable to find an I/O waveform of synchronous burst read/write with SLRD/SLWR asserted for the entire burst duration.
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Not yet rated
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06/17/11 |
Slave FIFO Address Lines for the CY7C68013 (FX2)
Figures 9-11 and 12 in the Technical Reference Manual present a small state machine on how to perform FIFO writes in asynchronous mode. Is it necessary to pass all the states in the state machine described in this section? Can I set FIFOADDR lines before one clock, perform a write cycle on the next clock, and subsequently change FIDOADDR lines in order to perform a write to a different endpoint?
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Not yet rated
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06/17/11 |
FX2 HID device unable to respond to the Get_Report_Descriptor request
I am using the bulkloop example as a basis to design a HID device using the FX2. I have defined the HID descriptor correctly as stated in the HID spec but the FX2 fails to respond to the GET_HID_DESCRIPTOR request. Do you have an example that shows how to design a HID device using FX2?
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(1/5) by 1
user
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06/17/11 |
EZ-USB FX2 Performance and Memory Size
We want to use the EZ-USB FX2 (CY7C68013-56PVC) chip on our demo board. We intend to use the chip's slave FIFO I/F in synchronous mode. The interface is coupled to an FPGA for further processing. This FPGA will then be the master for the slave FIFOs.
1) How can the local transfer rate of 96 MB/s be achieved? Is it necessary to use the chip in the GPIF mode? With 48 MHz and a 16 bit data bus this would require that Ican transfer a data word (16 bit) per IFCLK cycle. But that is not possible according to Chapter 9 of the Technical Reference Manual. When I look at your example waveforms it seems at least two cycles, or actually three with "State 4", are required. How does this fit into the performance of 96 MB/s? Is it possible to transfer 16-bit data words in one cycle? Or do I need to use one cycle for reading the data, and one cycle to check the FIFO flag and update the FIFO pointer? In this case I only have a performance of 48 MB/s.
2) The setup times for read and write are almost one clock cycle when working with the 48 MHz internal IFCLK. Do I need an additional cycle to set up SLWR or SLRD? Would this further decrease the performance.?I can't see how an inverted clock would help - it makes things even worse. Unless of course I may keep the SLWR or SLRD active during e.g. a packet read where I transfer a data word on each clock cycle!?If I use an external IFCLK, according to the data sheet I get better set-up times, but then I have stronger requirements for the hold time.
3) What is the exact amount of memory inside the chip for the Endpoints EP2, EP4, EP6, and EP8? Are endpoint buffers and endpoint FIFO two separate memory areas or one? Is there a physical memory space for both the FX2 memory space (containing endpoint buffers) and additional 4KB for the FIFOs?
The way I see it, two possbilities exist: a) FX2 memory has space for 3KB (e.g 6x buffers of 512 bytes each); or b) The FIFOs have a space of 4KB. According to your data sheet, an area of 2x 512 bytes in the FX2 memory space is reserved, which explains that a buffer for EP4 and EP8 only can be 512 bytes. The FIFO space (if it is extra space?) has a total of 4KB with no reserved areas, right?
4) When exactly are full and empty flags asserted? On a byte, 16-bit word, USB packet, or user defined packet size level? I need this exact information for both reads or writes to a slave FIFO endpoint. The technical reference manual fails to offer
precise information on that.
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06/17/11 |
Speed Up Slave FIFO Transfer (FX2)
Can I speed up a Slave FIFO transfer by asserting SLWR for consecutive IFCLK cycles, assuming the the programmable flag is continuously monitored?
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06/17/11 |
Achieving a Local Transfer Rate of 96MB/s in FX2
How can the local transfer rate of 96 MB/s be achieved?
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06/17/11 |
Slave FIFO/GPIF Usage With FX2
Can I use the CY7C68013's Slave FIFO and GPIF interface at the same time?
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06/17/11 |
External Logic Read of the CY7C68013
When using the C7C68013, is there a limit on the number of words/bytes the external logic can read from the FIFO at one time? For instance, when the empty flag is not asserted and the external logic has read 512 bytes from a quad buffered FIFO, does the external device need to stop and check the empty flag before beginning to start reading again?
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06/17/11 |
Read IOCTL failed Message in the Control Panel While Strobing SLWR Continuously - CY7C68013
When requesting a Bulk IN transfer using the EZ-USB Control Panel while strobing SLWR continuously, the response is a "Read IOCTL failed" message. Can some other part of the hardware be damaged?
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Not yet rated
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06/17/11 |
BL51: ERROR 107 (ADDRESS SPACE OVERFLOW)
I receive the following linker error when I compile and link my program:
*** ERROR L107: ADDRESS SPACE OVERFLOW
SPACE: DATA
SEGMENT: _DATA_GROUP_
LENGTH: 0014H
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Not yet rated
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06/17/11 |
About REVCTL
What is the REVCTL operation in EZ-USB FX2 and its use in general in the slave FIFO application, when the endpoint is set to auto mode?
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06/17/11 |
I2S interface support for FX2LP devices
Does FX2LP devices support I2S interface?
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06/17/11 |
AT2LP support for Selective suspend and Remote Wakeup
Does the AT2LP support Selective suspend and Remote Wakeup?
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06/17/11 |
FX2LP I2C operating speed is lesser than the expected value
In FX2LP’s I2C interface, when we select 400 kHz, we only get ~300 kHz bus speed. Similarly when we select 100 kHz, we get ~85 kHz. What is the reason?
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(2/5) by 1
user
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06/17/11 |
Using MLC (Multiple-Level Cell) Flash Nand with NX2LP
Can we use MLC (Multiple-Level Cell) Flash Nand with NX2LP?
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(1/5) by 1
user
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06/17/11 |
CY7C68300 / CY7C68300A - 24MHz crystal of the AT2
The manual states that a 24MHz crystal is recommended, but can another type of crystal be used?
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Not yet rated
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06/17/11 |
CY7C68300 / CY7C68300A - Driver Support for the EZ-USB AT2
Which Cypress driver supports the EZ-USB AT2?
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(5/5) by 1
user
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06/17/11 |
CY7C68300 / CY7C68300A - Alternate EEPROM for EZ-USB AT2
Can I use a different EEPROM with the EZ-USB AT2?
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Not yet rated
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06/17/11 |
Crystal requirements for the CY7C68300B/CY7C68301B/CY7C68320/CY7C68321 EZ-USB AT2LP parts
What are the crystal requirements for the CY7C68300B/CY7C68301B/CY7C68320/CY7C68321 EZ-USB AT2LP parts?
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Not yet rated
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06/17/11 |
Limitations of STA tool in PSoC Creator
What are all the limitations of Static Timing Analysis tool in PSoC Creator
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06/17/11 |
MLC support in NX2LP and Maximum Nand size
Does NX2LP-Flex support MLC flash? What is the Maximum size of NAND flash which it can support?
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06/17/11 |
Driver for CY3640 Thermometer application
Where can I get the drivers for Thermometer application available with CY3640?
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06/16/11 |
CY3640 Hi-Lo USB Programmer fails to program other M8 USB microcontrollers
I am trying to use Hi-Lo USB Programmer included in CY3640 to program other M8 USB microcontrollers, but it failed. Why?
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Not yet rated
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06/16/11 |
Low-speed D- is pulled up to 3.3V
The USB Spec says that low-speed D- is pulled up to 3.3V source through a 1.5K resistor. Some of your documents have a 7.5K instead. Why?
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Not yet rated
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06/16/11 |
Multiple interfaces with M8
Can a M8 device support multiple interfaces?
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06/16/11 |
Transmit 8 bytes every 1ms with a low-speed device
Can I transmit 8 bytes every 1ms with a low-speed device? The Spec says the fastest polling rate is 10ms.
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Not yet rated
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06/16/11 |
Higher Power consumption of TetraHub when in unconnected powered state
I have the TetraHub evaluation powered up and am measuring the current drawn by the device in connected and unconnected state. When I measure the current drawn by TetraHub and not connected to any host, it seems to be a lot more than what is measured when it is in a connected state. Power consumption is approximately 3.1W when unconnected. When connected power consumption goes down to approximately 1.2W. Why is the power consumption of TetraHub in a connected state more than it is when in an unconnected state?
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06/16/11 |
CY3500
What is the CY3500?
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Not yet rated
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06/15/11 |
Design for CY3650 fails on real silicon
Why does design work on the CY3650 development kit (or CY3651/CY3652), but does not work on real silicon?
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Not yet rated
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06/15/11 |
Using Sheet connector in PSoC Creator
What is a Sheet connector? How to use it?
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Not yet rated
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06/15/11 |
Displaying a Float Value on LCD in PSoC Creator
How do I convert a float value to ascii and display it on an LCD in PSoC Creator?
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(3.5/5) by 4
users
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06/15/11 |
Binding the driver manually for PSoC 3 FTK
How to bind the driver manually for PSoC3 First Touch Kit?
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Not yet rated
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06/15/11 |
Maximum allowable PLL output in PSoC Creator for PSoC 3
PSoC Creator does not allow PLL output to be set to 67 MHz. Why it is so? What is the way to set PLL output to maximum?
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Not yet rated
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06/15/11 |
Use of PSoC Creator for PSoC1
Can PSoC Creator be used for PSoC1 parts (CY8C2xxxx series parts)?
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Not yet rated
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06/15/11 |
Open source products used by PSoC Creator
What are the open source products which PSoC Creator use?
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06/15/11 |
ROM file download to CM8MON41
When using CM8MON41, why can't we download my ROM file correctly to the emulator?
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Not yet rated
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06/15/11 |
CY3650 Development Kit to program the 630xx/631xx parts
Is it possible to use the CY3650 Development Kit to program the 630xx/631xx parts?
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Not yet rated
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06/15/11 |
CY3650 working under Windows XP
Does the CY3650 (or CY3651/52) work under Win XP?
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Not yet rated
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06/15/11 |
SPI Interface with TetraHub
Can a processor with a SPI interface be used to program the TetraHub?
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Not yet rated
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06/15/11 |
Multiple USB devices connected to hub at the same time or during power-up
When I have multiple USB devices connected to a hub at the same time or during power-up of the hub, all the devices will have address 0. How will the host enumerate these devices?
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Not yet rated
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06/15/11 |
the unused GREEN# and AMBER# LED output pins of TetraHub
How should the unused GREEN# and AMBER# LED output pins of TetraHub be connected?
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Not yet rated
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06/15/11 |
What software comes with the Tetrahub reference design kit (CY4602)?
What software comes with the Tetrahub reference design kit (CY4602)?
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Not yet rated
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06/15/11 |
Input threshold of HX2 BUSPOWER pin
What is the input threshold of the HX2 BUSPOWER pin?
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Not yet rated
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06/15/11 |
TetraHub, QFN package overheating issue
Does the QFN package have any trick to avoid the heating issue?
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06/15/11 |
Minimum Supply Voltage to PSoC 1
What is the minimum operating supply voltage that can be provided to PSoC1 devices ?
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Not yet rated
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06/15/11 |
Default TT Mode of HX2
Why is the TetraHub set-up to default to single TT when it can support multiple TT?
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Not yet rated
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06/15/11 |
Win98 Drivers for TetraHub
Do you have drivers that can be used under Win 98 OS that support TetraHub functionality and do they support Multiple TT functionality?
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Not yet rated
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06/15/11 |
How are muliple Tetrahubs with same VID/PID addressed without having any serial number?
If serial numbers are not supported by TetraHub, how does the OS differentiate between multiple Tetrahubs with same VID/PID when plugged into the same USB host.
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Not yet rated
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06/15/11 |
Any schmitt triggers on TetraHub RESET pin?
Are there any schmitt triggers on TetraHub RESET pin? Any Rise and Fall time spec?
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Not yet rated
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06/15/11 |